Improving error correction codes for multiple-cell upsets in space applications
J Gracia-Moran, LJ Saiz-Adalid… - … Transactions on Very …, 2018 - ieeexplore.ieee.org
Currently, faults suffered by SRAM memory systems have increased due to the aggressive
CMOS integration density. Thus, the probability of occurrence of single-cell upsets (SCUs) or …
CMOS integration density. Thus, the probability of occurrence of single-cell upsets (SCUs) or …
Optimized fault-tolerant buffer design for network-on-chip applications
AC Pinheiro, JAN Silveira, DAB Tavares… - 2019 IEEE 10th Latin …, 2019 - ieeexplore.ieee.org
Newest technologies of integrated circuits manufacture allow billions of transistors arranged
in a single chip, which requires a communication architecture with high scalability and …
in a single chip, which requires a communication architecture with high scalability and …
Optimized buffer protection for network-on-chip based on Error Correction Code
Newest technologies of integrated circuits manufacture require a communication
architecture such as a Network-on-Chip (NoC). The NoC buffers are susceptible to Multiple …
architecture such as a Network-on-Chip (NoC). The NoC buffers are susceptible to Multiple …
Low power NoC buffer protection using error correction code
IT Katheresh, M Vinodhini - AIP Conference Proceedings, 2023 - pubs.aip.org
Network-on-Chip (NoC) is most widely used as a communication framework to connect
various Intellectual Properties (IPs) in an Integrated Circuit (IC). As technology scales down …
various Intellectual Properties (IPs) in an Integrated Circuit (IC). As technology scales down …
High performance static segment on-Chip memory for image processing applications
R Jothin, C Vasanthanayaki - Journal of Electronic Testing, 2018 - Springer
The performance of the processor core depends on the configuration parameters and
utilization of on-chip memory in multimedia applications such as image, video and audio …
utilization of on-chip memory in multimedia applications such as image, video and audio …
Design of Error Correction Engine Based on Flexible Unequal Error Control Code (FUEC) for Flash Memory Faults in Space Applications
G Amrutha Shree, VS Chakravarthi - Advances in Communication, Signal …, 2020 - Springer
Due to vast integration density in CMOS technology, faults in the embedded or external
memory have been increased. This manifests as single-cell upsets (SCU) and multiple cell …
memory have been increased. This manifests as single-cell upsets (SCU) and multiple cell …
Multiple fault mitigation in network-on-chip architectures through a bit-shuffling method
R Mercier - 2021 - theses.hal.science
Since several decades, fault tolerance has become a major research field due to transistor
shrinking and power scaling in system-on-chips. Especially, faults occurring to Network-on …
shrinking and power scaling in system-on-chips. Especially, faults occurring to Network-on …
High Performance Approximate Memories for Image Processing Applications
R Jothin, MP Mohamed - Journal of Electronic Testing, 2020 - Springer
Efficient utilization of on-chip Static Random Access Memory (SRAM) space is more
important on processor core design in modern Field Programmable Gate Array (FPGA) …
important on processor core design in modern Field Programmable Gate Array (FPGA) …
A virtual filter based fast assessment methodology for fault tolerant NoCs
J Jiao, D Han, Y Fu - IEICE Electronics Express, 2018 - jstage.jst.go.jp
Network on Chips (NoCs) as the compromising communication infrastructures in many-core
system, are suffering the serious Multi-Cell Upsets (MCU) impacts. To accelerate the …
system, are suffering the serious Multi-Cell Upsets (MCU) impacts. To accelerate the …