A survey on mapping and scheduling techniques for 3D Network-on-chip
SP Kaur, M Ghose, A Pathak, R Patole - Journal of Systems Architecture, 2024 - Elsevier
Abstract Network-on-chips (NoCs) have been widely employed in the design of
multiprocessor system-on-chips (MPSoCs) as a scalable communication solution. NoCs …
multiprocessor system-on-chips (MPSoCs) as a scalable communication solution. NoCs …
Application specific routing algorithms for networks on chip
In this paper we present a methodology to develop efficient and deadlock free routing
algorithms for Network-on-Chip (NoC) platforms which are specialized for an application or …
algorithms for Network-on-Chip (NoC) platforms which are specialized for an application or …
[图书][B] Design of cost-efficient interconnect processing units: Spidergon STNoC
M Coppola, MD Grammatikakis, R Locatelli… - 2020 - taylorfrancis.com
Streamlined Design Solutions Specifically for NoCTo solve critical network-on-chip (NoC)
architecture and design problems related to structure, performance and modularity …
architecture and design problems related to structure, performance and modularity …
Gossip noc--avoiding timing side-channel attacks through traffic management
C Reinbrecht, A Susin, L Bossuet… - 2016 IEEE Computer …, 2016 - ieeexplore.ieee.org
The wide use of Multi-processing systems-on-chip (MPSoCs) in embedded systems and the
trend to increase the integration between devices have turned these systems vulnerable to …
trend to increase the integration between devices have turned these systems vulnerable to …
Stochastic mechanics of graph rewriting
We propose an algebraic approach to stochastic graph-rewriting which extends the classical
construction of the Heisenberg-Weyl algebra and its canonical representation on the Fock …
construction of the Heisenberg-Weyl algebra and its canonical representation on the Fock …
Software controlled memories for scalable many-core architectures
LAD Bathen, ND Dutt - … and Real-Time Computing Systems and …, 2012 - ieeexplore.ieee.org
Technology scaling along with the ever evolving demand for media-rich software stacks
have motivated the need for many-core platforms. With the increase in compute power and …
have motivated the need for many-core platforms. With the increase in compute power and …
MMNoC: Embedding memory management units into network-on-chip for lightweight embedded systems
With the advent of the Internet-of-Things (IoT) era, the demand for lightweight embedded
systems is rapidly increasing. So far, ultra-low power (ULP) processors have been leading …
systems is rapidly increasing. So far, ultra-low power (ULP) processors have been leading …
Adaptive Dynamic On-chip Memory Management for FPGA-based reconfigurable architectures
In this paper, an adaptive architecture for dynamic management and allocation of on-chip
FPGA Block Random Access Memory (BRAM) resources is presented. This facilitates the …
FPGA Block Random Access Memory (BRAM) resources is presented. This facilitates the …
[PDF][PDF] Microarchitecture and implementation of Networks-on-Chip with a flexible concept for communication media sharing
FA Samman - 2010 - Citeseer
This thesis is based on my work that I have started in October 2006 at Fachgebiet
Mikroelektronische Systeme, Institut für Datentechnik, Fachbereich Elektrotechnik und …
Mikroelektronische Systeme, Institut für Datentechnik, Fachbereich Elektrotechnik und …
Multi-objective spiking neural network hardware mapping based on immune genetic algorithm
Abstract For the Spiking Neuron Network (SNN) systems, the hardware implementation has
unique advantages in terms of performance, energy, and scalability. The Networks-on-Chip …
unique advantages in terms of performance, energy, and scalability. The Networks-on-Chip …