Limits on fundamental limits to computation

IL Markov - Nature, 2014 - nature.com
An indispensable part of our personal and working lives, computing has also become
essential to industries and governments. Steady improvements in computer hardware have …

Pushing the level of abstraction of digital system design: A survey on how to program fpgas

ED Sozzo, D Conficconi, A Zeni, M Salaris… - ACM Computing …, 2022 - dl.acm.org
Field Programmable Gate Arrays (FPGAs) are spatial architectures with a heterogeneous
reconfigurable fabric. They are state-of-the-art for prototyping, telecommunications …

Domain-specific hardware accelerators

WJ Dally, Y Turakhia, S Han - Communications of the ACM, 2020 - dl.acm.org
Domain-specific hardware accelerators Page 1 48 COMMUNICATIONS OF THE ACM | JULY
2020 | VOL. 63 | NO. 7 contributed articles FROM THE SIMPLE embedded processor in your …

High-level synthesis for FPGAs: From prototyping to deployment

J Cong, B Liu, S Neuendorffer… - … on Computer-Aided …, 2011 - ieeexplore.ieee.org
Escalating system-on-chip design complexity is pushing the design community to raise the
level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of …

Convolution engine: balancing efficiency & flexibility in specialized computing

W Qadeer, R Hameed, O Shacham… - Proceedings of the 40th …, 2013 - dl.acm.org
This paper focuses on the trade-off between flexibility and efficiency in specialized
computing. We observe that specialized units achieve most of their efficiency gains by tuning …

COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications

J Zhao, L Feng, S Sinha, W Zhang… - 2017 IEEE/ACM …, 2017 - ieeexplore.ieee.org
High Level Synthesis (HLS) relies on the use of synthesis pragmas to generate digital
designs meeting a set of specifications. However, the selection of a set of pragmas depends …

Residue number systems: A new paradigm to datapath optimization for low-power and high-performance digital signal processing applications

CH Chang, AS Molahosseini… - IEEE circuits and …, 2015 - ieeexplore.ieee.org
Residue Number System (RNS) is a non-weighted number system which was proposed by
Garner back in 1959 to achieve fast implementation of addition, subtraction and …

FPDeep: Acceleration and load balancing of CNN training on FPGA clusters

T Geng, T Wang, A Sanaullah, C Yang… - 2018 IEEE 26th …, 2018 - ieeexplore.ieee.org
FPGA-based CNN accelerators have advantages in flexibility and power efficiency and so
are being deployed by a number of cloud computing service providers, including Microsoft …

mrFPGA: A novel FPGA architecture with memristor-based reconfiguration

J Cong, B Xiao - 2011 IEEE/ACM international symposium on …, 2011 - ieeexplore.ieee.org
In this paper, we introduce a novel FPGA architecture with memristor-based reconfiguration
(mrFPGA). The proposed architecture is based on the existing CMOS-compatible memristor …

The case for FPGA-based edge computing

C Xu, S Jiang, G Luo, G Sun, N An… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Edge Computing has emerged as a new computing paradigm dedicated for mobile
performance enhancement and energy efficiency purposes. Specifically, it benefits today's …