Transistor count reduction by gate merging

CM de Oliveira Conceição… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
A large set of ASICs uses much more transistors than its necessity, as they use a library of
cells with a limited amount of logic functions. This small number of logic functions in a …

Electrical Evaluation of Logic Network Generation Methods for On-the-Fly Supergate Design

H Kessler, M Muñoz, P Finkenauer… - Journal of Integrated …, 2021 - jics.org.br
Recent developments in electronic design automation tools vastly reduce the design cost of
supergates, enabling an alternative approach to logic synthesis. Despite many design …

Transistor Reordering for Electrical Improvement in CMOS Complex Gates

MM Muñoz, H Kessler, M Porto… - 2022 35th SBC …, 2022 - ieeexplore.ieee.org
As the automated design of supergates becomes possible, techniques to improve their
electrical characteristics grow in relevance. Among the design choices, the order of …