Progress and challenges in VLSI placement research

IL Markov, J Hu, MC Kim - … of the International Conference on Computer …, 2012 - dl.acm.org
Given the significance of placement in IC physical design, extensive research studies
performed over the last 50 years addressed numerous aspects of global and detailed …

Force-directed algorithms for schematic drawings and placement: A survey

SH Cheong, YW Si - Information Visualization, 2020 - journals.sagepub.com
Force-directed algorithms have been developed over the last 50 years and used in many
application fields, including information visualisation, biological network visualisation …

Implementation and extensibility of an analytic placer

AB Kahng, Q Wang - Proceedings of the 2004 international symposium …, 2004 - dl.acm.org
Automated cell placement is a critical problem in VLSI physical design. New analytical
placement methods that simultaneously spread cells and optimize wirelength have recently …

DREAMPlace 4.0: Timing-driven global placement with momentum-based net weighting

P Liao, S Liu, Z Chen, W Lv, Y Lin… - 2022 Design, Automation …, 2022 - ieeexplore.ieee.org
Timing optimization is critical to integrated circuit (IC) design closure. Existing global
placement algorithms mostly focus on wirelength optimization without considering timing. In …

Sensitivity guided net weighting for placement driven synthesis

TY Wang, JL Tsai, CCP Chen - … of the 2004 international symposium on …, 2004 - dl.acm.org
Net weighting is a key technique in large scale timing driven placement, which plays a
crucial role for deep submicron physical synthesis and timing closure. A popular way to …

Dreamplace 4.0: Timing-driven placement with momentum-based net weighting and lagrangian-based refinement

P Liao, D Guo, Z Guo, S Liu, Y Lin… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Optimizing timing is critical to the design closure of integrated circuits (ICs). However, most
existing algorithms for circuit placement focus on the optimization of wirelength instead of …

Techniques for fast physical synthesis

CJ Alpert, SK Karandikar, Z Li, GJ Nam… - Proceedings of the …, 2007 - ieeexplore.ieee.org
The traditional purpose of physical synthesis is to perform timing closure, ie, to create a
placed design that meets its timing specifications while also satisfying electrical, routability …

Clock tree resynthesis for multi-corner multi-mode timing closure

S Roy, PM Mattheakis, L Masse-Navette… - Proceedings of the 2014 …, 2014 - dl.acm.org
With aggressive technology scaling and complex design scenarios, timing closure has
become a challenging and tedious job for the designers. Timing violations persist for multi …

How accurately can we model timing in a placement engine?

A Chowdhary, K Rajagopal, S Venkatesan… - Proceedings of the …, 2005 - dl.acm.org
This paper presents a novel placement algorithm for timing optimization based on a new
and powerful concept, which we term differential timing analysis. Recognizing that accurate …

An analytic placer for mixed-size placement and timing-driven placement

AB Kahng, Q Wang - … on Computer Aided Design, 2004. ICCAD …, 2004 - ieeexplore.ieee.org
We extend the APlace wirelength-driven standard-cell analytic placement framework of AA
Kennings and IL Markov (2002) to address timing-driven and mixed-size (" boulders and …