A survey of timing verification techniques for multi-core real-time systems

C Maiza, H Rihani, JM Rivas, J Goossens… - ACM Computing …, 2019 - dl.acm.org
This survey provides an overview of the scientific literature on timing verification techniques
for multi-core real-time systems. It reviews the key results in the field from its origins around …

Memory interference characterization between CPU cores and integrated GPUs in mixed-criticality platforms

R Cavicchioli, N Capodieci… - 2017 22nd IEEE …, 2017 - ieeexplore.ieee.org
Most of today's mixed criticality platforms feature Systems on Chip (SoC) where a multi-core
CPU complex (the host) competes with an integrated Graphic Processor Unit (iGPU, the …

A survey of techniques for reducing interference in real-time applications on multicore platforms

T Lugo, S Lozano, J Fernández, J Carretero - IEEE Access, 2022 - ieeexplore.ieee.org
This survey reviews the scientific literature on techniques for reducing interference in real-
time multicore systems, focusing on the approaches proposed between 2015 and 2020. It …

Holistic resource allocation for multicore real-time systems

M Xu, LTX Phan, HY Choi, Y Lin, H Li… - 2019 IEEE Real-Time …, 2019 - ieeexplore.ieee.org
This paper presents CaM, a holistic cache and memory bandwidth resource allocation
strategy for multicore real-time systems. CaM is designed for partitioned scheduling, where …

Temporal isolation of hard real-time applications on many-core processors

Q Perret, P Maurere, E Noulard… - 2016 IEEE Real …, 2016 - ieeexplore.ieee.org
Many-core processors offer massively parallel computation power representing a good
opportunity for the design of highly integrated avionics systems. Such designs must face …

[PDF][PDF] PREM-based optimal task segmentation under fixed priority scheduling

MR Soliman, R Pellizzoni - … on Real-Time Systems (ECRTS 2019 …, 2019 - drops.dagstuhl.de
Recently, a large number of works have discussed scheduling tasks consisting of a
sequence of memory phases, where code and data are moved between main memory and …

Dna: Dynamic resource allocation for soft real-time multicore systems

R Gifford, N Gandhi, LTX Phan… - 2021 IEEE 27th Real …, 2021 - ieeexplore.ieee.org
Modern latency-sensitive and real-time systems often use multi-core platforms; thus, tasks
on different cores share certain hardware resources, such as the memory bus and certain …

Fixed-priority memory-centric scheduler for cots-based multiprocessors

G Schwäricke, T Kloda, G Gracioli… - … Conference on Real …, 2020 - drops.dagstuhl.de
Memory-centric scheduling attempts to guarantee temporal predictability on commercial-off-
the-shelf (COTS) multiprocessor systems to exploit their high performance for real-time …

Contending memory in heterogeneous SoCs: Evolution in NVIDIA Tegra embedded platforms

N Capodieci, R Cavicchioli, IS Olmedo… - 2020 IEEE 26th …, 2020 - ieeexplore.ieee.org
Modern embedded platforms are known to be constrained by size, weight and power
(SWaP) requirements. In such contexts, achieving the desired performance-per-watt target …

IXIAM: ISA EXtension for Integrated Accelerator Management

B Peccerillo, E Cheshmikhani, M Mannino… - IEEE …, 2023 - ieeexplore.ieee.org
During the last few years, hardware accelerators have been gaining popularity thanks to
their ability to achieve higher performance and efficiency than classic general-purpose …