Benchmark figure of merit extensions for low jitter phase locked loops inspired by new PLL architectures
W Bae - IEEE Access, 2022 - ieeexplore.ieee.org
A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …
powerful indicator to compare and to normalize performance of different PLL designs …
A Fractional-N Digital MDLL With Background Two-Point DTC Calibration
This article presents a fractional-digital multiplying delay-locked loop (MDLL) that employs a
digital-to-time converter (DTC) to control the reference injection for the fractional-operation …
digital-to-time converter (DTC) to control the reference injection for the fractional-operation …
29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving-60dBc Fractional Spur
Ring oscillator (RO)-based frequency synthesizers enable cost-efficient and scaling-friendly
implementation, but also result in worse phase noise compared to LC-based alternatives …
implementation, but also result in worse phase noise compared to LC-based alternatives …
A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a 62.1-dBc Fractional Spur
This article presents a 7-GHz fractional-N digital phase-locked loop (DPLL) without any
digital pre-distortion (DPD) on the integral nonlinearity (INL) of the digital-to-time converter …
digital pre-distortion (DPD) on the integral nonlinearity (INL) of the digital-to-time converter …
A deep reinforcement learning framework for high-dimensional circuit linearization
C Rong, J Paramesh, LR Carley - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Despite the successes of Reinforcement Learning (RL) in recent years, tasks that require
exploring over long trajectories with limited feedback and searching in high-dimensional …
exploring over long trajectories with limited feedback and searching in high-dimensional …
A 3.2-to-3.8 GHz harmonic-mixer-based dual-feedback fractional-N PLL achieving-65 dBc in-band fractional spur
A harmonic-mixer-based dual-feedback loop architecture for fractional frequency synthesis
is proposed in this letter. By performing frequency subtraction instead of frequency division …
is proposed in this letter. By performing frequency subtraction instead of frequency division …
Digital Phase-Locked Loops: Exploring Different Boundaries
This article examines the research area of digital phase-locked loops (DPLLs), a critical
component in modern electronic systems, from wireless communication devices to RADAR …
component in modern electronic systems, from wireless communication devices to RADAR …
A high-pass shaped LMS algorithm based predistortion technique for fractional-N BB-DPLLs
TM Vo - Microelectronics Journal, 2024 - Elsevier
In this paper, we prove that rather than the second-order Δ Σ modulator (DSM) as typically
believed using the first-order one yields a faster convergence for the linear-piecewise …
believed using the first-order one yields a faster convergence for the linear-piecewise …
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1 dBc Fractional Spur and 143.7 fs Integrated Jitter
Modern wireless transceivers and FMCW radar systems are demanding stringent
specifications on PLL integrated jitter and spur performance for lower EVM and higher …
specifications on PLL integrated jitter and spur performance for lower EVM and higher …
A 2.3-3.9 GHz fractional-N frequency synthesizer with charge pump and TDC calibration for reduced reference and fractional spurs
J Jiang, T Yan, D Zhou, AI Karsilayan… - 2021 IEEE Radio …, 2021 - ieeexplore.ieee.org
A 2.3-3.9 GHz fractional-N phase locked loop (PLL) with charge pump and a time-to-digital
converter (TDC) based calibration for reference and fractional spurs reduction suitable for …
converter (TDC) based calibration for reference and fractional spurs reduction suitable for …