A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking
This article presents a fractional-N frequency synthesizer architecture that is able to
overcome the limitations of conventional bang-bang phase-locked loops. A digital …
overcome the limitations of conventional bang-bang phase-locked loops. A digital …
A 0.65-V 12–16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM
This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …
Benchmark figure of merit extensions for low jitter phase locked loops inspired by new PLL architectures
W Bae - IEEE Access, 2022 - ieeexplore.ieee.org
A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …
powerful indicator to compare and to normalize performance of different PLL designs …
A 2.4-GHz reference-sampling phase-locked loop that simultaneously achieves low-noise and low-spur performance
J Sharma, H Krishnaswamy - IEEE Journal of Solid-State …, 2019 - ieeexplore.ieee.org
Dividerless synthesizers such as sub-sampling phase-locked loops (PLLs) and injection-
locked clock multipliers have demonstrated some of the lowest jitters for a given power …
locked clock multipliers have demonstrated some of the lowest jitters for a given power …
Low-power and low-noise millimeter-wave SSPLL with subsampling lock detector for automatic dividerless frequency acquisition
An 8.8-mW, low-noise, 40.5-GHz frequency synthesizer is proposed. The synthesizer system
consists of a subsampling phase-locked loop (SSPLL) with 100-MHz crystal reference, a …
consists of a subsampling phase-locked loop (SSPLL) with 100-MHz crystal reference, a …
A sub-mW 2.4-GHz active-mixer-adopted sub-sampling PLL achieving an FoM of− 256 dB
DG Lee, PP Mercier - IEEE Journal of Solid-State Circuits, 2019 - ieeexplore.ieee.org
An active-mixer-adopted sub-sampling phase-locked loop (AMASS-PLL) is presented that
replaces the passive-mixer-like sample-and-hold switches and charge pump (CP) of a sub …
replaces the passive-mixer-like sample-and-hold switches and charge pump (CP) of a sub …
A Type-I Sub-Sampling PLL With a Footprint and −255-dB FOM
A Sharkia, S Mirabbasi… - IEEE Journal of Solid-State …, 2018 - ieeexplore.ieee.org
A dual-loop LC-voltage-controlled oscillator (VCO) based frequency synthesizer, composed
of an all-digital frequency-locked loop (ADFLL) and a voltage-mode, type-I, subsampling …
of an all-digital frequency-locked loop (ADFLL) and a voltage-mode, type-I, subsampling …
Reference oversampling PLL achieving− 256-dB FoM and− 78-dBc reference spur
This article presents a low jitter, low power, low reference spur LC oscillator-based reference
oversampling digital phase locked loop (OSPLL). The proposed reference oversampling …
oversampling digital phase locked loop (OSPLL). The proposed reference oversampling …
A 12.9-to-15.1-GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping
This work introduces a bang-bang fractional-phase-locked loop with quantization noise
shaping that overcomes the classical noise limit of a standard bang-bang phase detector. An …
shaping that overcomes the classical noise limit of a standard bang-bang phase detector. An …
A 10-mW mm-wave phase-locked loop with improved lock time in 28-nm FD-SOI CMOS
M Abdulaziz, T Forsberg, M Törmänen… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
This paper presents a millimeter-wave (mm-wave) phase-locked loop (PLL), with an output
frequency centered at 54.65 GHz. It demonstrates a mode-switching architecture that …
frequency centered at 54.65 GHz. It demonstrates a mode-switching architecture that …