The movement toward 3D fabrication coupled with Network-on-Chip (NoC) aims to improve
area, performance, power, and scalability of many-core systems. However, reliability issue …

Monolithic 3D (M3D) integration provides massive vertical integration through the use of
nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling …

Emerging 3D integrated circuits (ICs) employ 3D network-on-chip (NoC) to improve power,
performance, and scalability. The NoC Simulator uses the microarchitecture parameters to …

Near Field Inductive Coupling (NFIC) enables design of energy efficient and robust three-
dimensional (3D) manycore systems. The associated design challenges and the trade-offs …

3D Network-on-Chip (3D NoC) enables design of high-performance and energy-efficient
manycore computing platforms. Two of the commonly used vertical interconnection …

In this paper, a dual-frequency compact power divider based on silicon via (TSV) is
proposed. The matrix analysis method is used to convert the microstrip structure into Π-type …

In comparison with through-silicon vias (TSVs) used in 3-D integrated circuits (3D ICs),
nanoscale interlayer via (ILV) employed in monolithic 3D ICs offers higher integration …

One of the fundamental challenges to the performance gain in advanced semiconductor
technology is aging-induced delay degradation of transistors, which consequently increases …

A 3D network-on-chip (3D NoC) is an enabler for the design of high-performance and
energy-efficient manycore chips. Most popular 3D NoCs utilize the Through-Silicon-Via …

With the increase in number and complexity of cores and components in CMPs and SoCs, a
highly structured and efficient on-chip communication network is required to achieve high …