Analysis of on-chip inductance effects for distributed RLC interconnects
K Banerjee, A Mehrotra - IEEE Transactions on computer …, 2002 - ieeexplore.ieee.org
This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC
interconnects that takes the effect of both the series resistance and the output parasitic …
interconnects that takes the effect of both the series resistance and the output parasitic …
On-chip power supply network optimization using multigrid-based technique
K Wang, M Marek-Sadowska - Proceedings of the 40th annual Design …, 2003 - dl.acm.org
In this paper, we present a novel multigrid-based technique for on-chip power supply
network optimization. We reduce a large-scale network to a much coarser one which can be …
network optimization. We reduce a large-scale network to a much coarser one which can be …
VoxHenry: FFT-accelerated inductance extraction for voxelized geometries
VoxHenry, a fast Fourier transform (FFT)-accelerated integral-equation-based simulator for
extracting frequency-dependent inductances and resistances of structures discretized by …
extracting frequency-dependent inductances and resistances of structures discretized by …
INDUCTWISE: Inductance-wise interconnect simulator and extractor
We develop a robust, efficient, and accurate tool, which integrates inductance extraction and
simulation, called INDUCTWISE. This paper advances the state-of-the-art inductance …
simulation, called INDUCTWISE. This paper advances the state-of-the-art inductance …
Expression of Concern: Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance
M Mondal, Y Massoud - ICCAD-2005. IEEE/ACM International …, 2005 - ieeexplore.ieee.org
The increasing demand for high performance ICs and system on chip necessitates reliable
methodologies for reducing pessimism in chip design. In this paper, we investigate how the …
methodologies for reducing pessimism in chip design. In this paper, we investigate how the …
Inductive properties of high-performance power distribution grids
AV Mezhiba, EG Friedman - IEEE Transactions on Very Large …, 2002 - ieeexplore.ieee.org
The design of high integrity, area efficient power distribution grids has become of practical
importance as the portion of on-chip interconnect resources dedicated to power distribution …
importance as the portion of on-chip interconnect resources dedicated to power distribution …
Security-driven placement and routing tools for electromagnetic side-channel protection
Side-channel analysis (SCA) attacks are major threats to hardware security. Upon this
security threat, various countermeasures at different design layers have been proposed …
security threat, various countermeasures at different design layers have been proposed …
Inductance 101: Analysis and design issues
K Gala, D Blaauw, J Wang, V Zolotov… - Proceedings of the 38th …, 2001 - dl.acm.org
With operating frequencies approaching the gigahertz range, inductance is becoming an
increasingly important consideration in the design and analysis of on-chip interconnect. In …
increasingly important consideration in the design and analysis of on-chip interconnect. In …
Automatic on-chip clock network optimization for electromagnetic side-channel protection
Commercial electronic design automation (EDA) tools typically focus on optimizing the
power, area, and speed of integrated circuits (ICs). They rarely consider hardware security …
power, area, and speed of integrated circuits (ICs). They rarely consider hardware security …
Technology trends in power-grid-induced noise
SR Nassif, O Fakhouri - Proceedings of the 2002 international workshop …, 2002 - dl.acm.org
With technology scaling, the trend for high performance integrated circuits is towards higher
power dissipation, higher operating frequency and lower power supply voltages. This …
power dissipation, higher operating frequency and lower power supply voltages. This …