[PDF][PDF] A review on reversible logic gates and their implementation

R Garipelly, PM Kiran, AS Kumar - International Journal of Emerging …, 2013 - academia.edu
Reversible logic is one of the most vital issue at present time and it has different areas for its
application, those are low power CMOS, quantum computing, nanotechnology …

Efficient approaches for designing reversible binary coded decimal adders

AK Biswas, MM Hasan, AR Chowdhury… - Microelectronics journal, 2008 - Elsevier
Reversible logic has become one of the most promising research areas in the past few
decades and has found its applications in several technologies; such as low-power CMOS …

[PDF][PDF] A brief overview of reversible logic gate and reversible circuits

S Singh, A Choudhary, MK Jain - International journal of Electronics …, 2019 - csjournals.com
Due course of application in various domains like Low power CMOS Technology,
Nanotechnology and Quantum Computing lead Reversible logic to be a emerging …

[PDF][PDF] Design of reversible sequential circuit using reversible logic synthesis

MB Ali, MM Hossin, ME Ullah - International Journal of VLSI Design …, 2011 - academia.edu
Reversible logic is one of the most vital issue at present time and it has different areas for its
application, those are low power CMOS, quantum computing, nanotechnology …

Design of efficient binary-coded decimal adder in QCA technology with a regular clocking scheme

I Gassoumi, L Touil, A Mtibaa - Computers and Electrical Engineering, 2022 - Elsevier
Quantum-dot cellular automata (QCA) is a promising nanotechnology that offers an
alternative to complementary metal-oxide-semiconductor (CMOS) technology. Nanoscale …

Review on reversible logic circuits and its application

R Khanam, A Rahman - 2017 International Conference on …, 2017 - ieeexplore.ieee.org
Reversible gate has been one of the emerging research area that ensure continual process
of innovation trends that explore and utilizes the resources. The reversible gate is sparked …

Design of a high-efficient MSD adder

J Peng, R Shen, X Ping - The Journal of Supercomputing, 2016 - Springer
Carry propagation delay is a big obstacle to improve the addition efficiency in computer
system. And the more data bits the operands have, the delay is more serious. As data bits of …

[PDF][PDF] Optimized design of BCD adder and Carry skip BCD adder using reversible logic gates

HR Bhagyalakshmi, MK Venkatesha - International journal on computer …, 2011 - ttcenter.ir
Reversible logic is very essential for the construction of low power, low loss computational
structures which are very essential for the construction of arithmetic circuits used in quantum …

FPGA-specific decimal sign-magnitude addition and subtraction

M Vázquez, E Todorovich - International Journal of Electronics, 2016 - Taylor & Francis
The interest in sign-magnitude (SM) representation in decimal numbers lies in the IEEE 754-
2008 standard, where the significand in floating-point numbers is coded as SM. However …

[PDF][PDF] FPGA implementation of low power hardware efficient flagged binary coded decimal adder

KN Vijeyakumar, V Sumathy, AD Babu… - International Journal of …, 2012 - Citeseer
This paper presents a novel architecture for hardware efficient binary represented decimal
addition. We extend the two operand ripple carry addition by one with the third input being …