High-level synthesis hardware design for fpga-based accelerators: Models, methodologies, and frameworks

RS Molina, V Gil-Costa, ML Crespo, G Ramponi - IEEE Access, 2022 - ieeexplore.ieee.org
Hardware accelerators based on field programmable gate array (FPGA) and system on chip
(SoC) devices have gained attention in recent years. One of the main reasons is that these …

An hardware accelerator design of Mobile-Net model on FPGA

S MV, M Rao - Proceedings of the Second International Conference …, 2022 - dl.acm.org
Domain specific hardware architectures and hardware accelerators have been a vital part of
modern system design. Especially for math intensive applications involving tasks related to …

Adaptive Pre-Processing for Neural Network Hardware Deployment

D Del Gaizo, F De Palo, F Cipriani… - 2023 IEEE 33rd …, 2023 - ieeexplore.ieee.org
Neural Networks are gaining popularity in the signal processing (SP) field. In radar SP,
micro-Doppler based classification with Convolutional Neural Networks has shown state-of …

[图书][B] Efficient Hardware Implementation of Deep Learning Networks Based on the Convolutional Neural Network

A Ansari - 2023 - search.proquest.com
Image classification, speech processing, autonomous driving, and medical diagnosis have
made the adoption of Deep Neural Networks (DNN) mainstream. Many deep networks such …

SoC-based FPGA architecture for image analysis and other highly demanding applications

RS Molina - 2023 - arts.units.it
Nowadays, the development of algorithms focuses on performance-efficient and energy-
efficient computations. Technologies such as field programmable gate array (FPGA) and …

VGG16 hardware design and implementation for CNN in image recognition

Y Tan, L Wu, Z Zhang, X Zhang… - … , and Computing (ICINC …, 2024 - spiedigitallibrary.org
Convolutional neural networks (CNN) are computationally intensive algorithms with rich
application scenarios. In some applications, convolutional neural networks need to be …