An overlay for rapid fpga debug of machine learning applications

DH Noronha, R Zhao, Z Que, J Goeders… - … Conference on Field …, 2019 - ieeexplore.ieee.org
FPGAs show promise as machine learning accelerators for both training and inference.
Designing these circuits on reconfigurable technology is challenging, especially due to bugs …

Boosting domain-specific debug through inter-frame compression

Z Nafziger, M Chua, DH Noronha… - … Conference on Field …, 2022 - ieeexplore.ieee.org
Acceleration of machine learning models is proving to be an important application for
FPGAs. Unfortunately, debugging such models during training or inference is difficult …

Dynamic debugging of circuits

U Merugu, M Sankroj, SB Kotamraju - US Patent 10,816,598, 2020 - Google Patents
A system for debugging circuits includes an integrated circuit configured to implement a
circuit under test and a logic analyzer controller coupled to the circuit under test. The system …

Cycle-Accurate Debugging of Multi-clock Reconfigurable Systems

G Akgün, A Podlubne, F Wegener… - 2019 International …, 2019 - ieeexplore.ieee.org
This paper presents a cycle accurate intrusive debugging methodology for embedded
designs having multiple-clock domains. In this methodology, a cycle-accurate lossless …

Scalable scan architecture for multi-circuit block arrays

N Patel, A Majumdar, PT Chaudhuri - US Patent 11,639,962, 2023 - Google Patents
US11639962B1 - Scalable scan architecture for multi-circuit block arrays - Google Patents
US11639962B1 - Scalable scan architecture for multi-circuit block arrays - Google Patents …

Cycle-Accurate and Cycle-Reproducible Debugging of Embedded Designs Using Artificial Intelligence

D Göhringer - 2018 28th International Conference on Field …, 2018 - ieeexplore.ieee.org
This research work presents an intrusive methodology for debugging of embedded designs
by using artificial intelligence technique. In this methodology, a cycle-accurate lossless …