[PDF][PDF] A novel 3-D-IC test architecture-a review

R Karthick, M Sundararajan - International Journal of Engineering …, 2018 - researchgate.net
Here, this paper completely examines the crosstalk noise of Through-Silicon-Vias (TSVs) in
high speed operations by means of a novel 3-Dimensional-IC Test structural design. In order …

Optimization of Built-In Self-Test test chain configuration in 2.5 D Integrated Circuits Using Constrained Multi-Objective Evolutionary Algorithm

Z Yang, L Deng, C Li, L Zhang - Engineering Applications of Artificial …, 2025 - Elsevier
5 D Integrated Circuit (2.5 D IC) is an advanced packaging technology. This technology
facilitates the dense integration of multiple dies by adding passive components to the silicon …

Scan-based testing of post-bond silicon interposer interconnects in 2.5-D ICs

R Wang, K Chakrabarty, B Eklow - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
2.5-D integration is emerging as the precursor to stacked 3-D ICs. Since the silicon
interposer and micro-bumps in 2.5-D integration can suffer from fabrication and assembly …

Built-in self-test and test scheduling for interposer-based 2.5 D IC

R Wang, K Chakrabarty, S Bhawmik - ACM Transactions on Design …, 2015 - dl.acm.org
Interposer-based 2.5 D integrated circuits (ICs) are seen today as a precursor to 3D ICs
based on through-silicon vias (TSVs). All the dies and the interposer in a 2.5 D IC must be …

Interconnect testing and test-path scheduling for interposer-based 2.5-D ICs

R Wang, K Chakrabarty… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Interposer-based 2.5-D integrated circuits (ICs) are seen today as a first step toward the
eventual industry adoption of 3-D ICs based on through-silicon vias (TSVs). The TSVs and …

Built-in test and diagnosis for TSVs with different placement topologies and crosstalk impact ranges

WH Hsu, MA Kochte, KJ Lee - IEEE Transactions on Computer …, 2016 - ieeexplore.ieee.org
Through silicon vias (TSVs) play an important role in 3-D chip integration. Effective and
efficient testing for correct operation of TSVs is essential for 3-D integrated circuit design …

Test methodology automation for multi-die package realization

R Gulve, DP Bade, S Kulkarni… - … Test Conference India …, 2022 - ieeexplore.ieee.org
Technological advancements in multi-die, chiplet, or other 3D architecture design are
required to fulfill the high computational power needed for chips in the AI/meta world …

Testing of interposer-based 2.5 D integrated circuits

R Wang, K Chakrabarty - 2016 IEEE International Test …, 2016 - ieeexplore.ieee.org
Interposer-based 2.5 D integrated circuits (ICs) are seen today as a precursor to 3D ICs
based on through-silicon vias (TSVs). All the dies and the interposer in a 2.5 D IC must be …

3D-IC test architecture for TSVs with different impact ranges of crosstalk faults

WH Hsu, MA Kochte, KJ Lee - 2016 International Symposium …, 2016 - ieeexplore.ieee.org
Through Silicon Vias (TSV) play an important role in 3D chip integration. Its features include:
providing vertical interconnection, decreasing the area of routing, and increasing the …

Built-in self-test for interposer-based 2.5 D ICs

R Wang, K Chakrabarty… - 2014 IEEE 32nd …, 2014 - ieeexplore.ieee.org
Interposer-based 2.5 D integrated circuits (ICs) are seen today as a precursor to 3D ICs
based on through-silicon vias (TSVs). All the dies and the interposer in a 2.5 D IC must be …