Area efficient implementation of FSK receiver on Xilinx Zynq FPGA

Area efficient SDR receiver without and with dynamic partial reconfiguration

TT Reddy, BK Madhavi… - International Journal of …, 2018 - inderscienceonline.com
Dynamic partial reconfiguration (DPR) technique is a very efficient for low-cost field
programmable gate array (FPGA) for realising several application categories like signal …
相关文章 所有 2 个版本