A survey on analog-to-digital converter integrated circuits for miniaturized high resolution ultrasonic imaging system

D Chen, X Cui, Q Zhang, D Li, W Cheng, C Fei, Y Yang - Micromachines, 2022 - mdpi.com
As traditional ultrasonic imaging systems (UIS) are expensive, bulky, and power-consuming,
miniaturized and portable UIS have been developed and widely utilized in the biomedical …

A 0.6-V 13-bit 20-MS/s two-step TDC-assisted SAR ADC with PVT tracking and speed-enhanced techniques

M Zhang, CH Chan, Y Zhu… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
This article presents a low power-supplied 13-bit 20-MS/s time-to-digital converter (TDC)-
assisted successive approximation register (SAR) analog-to-digital converter (ADC). In this …

A temperature-stabilized single-channel 1-GS/s 60-dB SNDR SAR-assisted pipelined ADC with dynamic Gm-R-based amplifier

W Jiang, Y Zhu, M Zhang, CH Chan… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
A temperature-stabilized 12-bit single-channel successive approximation register (SAR)-
assisted pipelined analog-to-digital converter (ADC) running at 1 GS/s with Nyquist signal to …

A Discrete-Time Audio Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques

S Ma, L Liu, T Fang, J Liu, N Wu - IEEE Journal of Solid-State …, 2019 - ieeexplore.ieee.org
This article presents a discrete-time secondorder ΔΣ modulator for the audio applications. In
this modulator, a novel dynamic amplifier is proposed to realize the switched-capacitor (SC) …

A 12-bit 1 GS/s RF sampling pipeline-SAR ADC with harmonic injecting cross-coupled pair achieving 7.5 fj/conv-step

L Fang, X Wen, T Fu, P Gui - … on Circuits and Systems I: Regular …, 2022 - ieeexplore.ieee.org
We present an RF sampling 1 GS/s 12-bit single-channel successive approximation register
(SAR) assisted pipeline analog to digital converter (ADC). A novel Harmonic-injecting Cross …

A 91.0-dB SFDR single-coarse dual-fine pipelined-SAR ADC with split-based background calibration in 28-nm CMOS

Y Cao, S Zhang, T Zhang, Y Chen… - … on Circuits and …, 2020 - ieeexplore.ieee.org
This paper presents a single-coarse dual-fine architecture that improves energy-efficiency of
pipelined-SAR analog-to-digital converters (ADCs). A coarse and fast sub-ADC is used to …

A two-step ADC with a continuous-time SAR-based first stage

L Shen, Y Shen, Z Li, W Shi, X Tang, S Li… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
This article presents a two-step analog-to-digital converter (ADC) that operates its first-stage
successive approximation register (SAR) ADC in the continuous-time (CT) domain. It avoids …

A 13b 600-675MS/s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Residue Amplifier

X Guo, R Chen, Z Chen, B Li - IEEE Journal of Solid-State …, 2022 - ieeexplore.ieee.org
This article presents a 13-b high-speed pipelined-successive-approximation-register
(pipelined-SAR) analog-to-digital converter (ADC). By utilizing the comparator metastability …

A reconfigurable 8-to-12-b 10-MS/s energy-efficient two-step ADC

X Li, Y Liang - Microelectronics Journal, 2023 - Elsevier
This paper proposes a reconfigurable and energy-efficient 8-to-12-bit 10 MS/s analog-to-
digital-converter (ADC), which adopts the SAR-TDC architecture to enhance the power …

A 52.5-dB 2 Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC

H Zhao, M Zhang, Y Zhu, RP Martins… - IEEE Journal of Solid …, 2023 - ieeexplore.ieee.org
This article presents a high-speed 5-bit/cycle successive-approximation register (SAR)
analog-to-digital converter (ADC) facilitated by a linearized configurable voltage-to-time …