Area-Efficient Iterative Logarithmic Approximate Multipliers for IEEE 754 and Posit Numbers

S Kim, CJ Norris, JI Oelund… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
The IEEE 754 standard for floating-point (FP) arithmetic is widely used for real numbers.
Recently, a variant called posit was proposed to improve the precision around 1 and− 1 …

An approximate and iterative posit multiplier architecture for FPGAs

CJ Norris, S Kim - … Symposium on Circuits and Systems (ISCAS …, 2021 - ieeexplore.ieee.org
Recently, many applications have demanded cheaper and faster arithmetic while providing
a wider dynamic range than the popular IEEE 754 floating-point (FP) arithmetic. As a result …

Risk-5: Controlled approximations for RISC-V

I Felzmann, J Fabrício Filho… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Approximate Computing offers enhanced energy efficiency by exploring quality relaxation
on applications. Application-agnostic hardware-level techniques can provide high benefits …

FPGA implementation of breast cancer detection using SVM linear classifier

HS Laxmisagar, MC Hanumantharaju - Multimedia Tools and Applications, 2023 - Springer
Abstract The Support Vector Machine (SVM) can be used to perform linear and nonlinear
operations to solve regression and classification problems. The SVM algorithm is …

ILAFD: Accuracy-Configurable Floating-Point Divider Using an Approximate Reciprocal and an Iterative Logarithmic Multiplier

J Oelund, S Kim - Proceedings of the Great Lakes Symposium on VLSI …, 2023 - dl.acm.org
Approximate computing provides benefits in the logic area, latency, and/or power without
significantly affecting the outputs of some applications. Various approximate computing …

A Use Case of Iterative Logarithmic Floating-Point Multipliers: Accelerating Histogram Stretching on Programmable SoC

CJ Norris, S Kim - … Symposium on Circuits and Systems (ISCAS …, 2023 - ieeexplore.ieee.org
Programmable system-on-chip (SoC) platforms often have a hard-core processor and
programmable logic for heterogeneous computing. A custom hardware design implemented …

A study on VLSI implementation of image enhancement techniques

AF Aklak, MY Pugazhenthi… - … and Computation: Practice …, 2022 - Wiley Online Library
In real‐time, the images captured are not always appreciable for visual perception. The
quality of the image relies on the illumination condition. Contrast enhancement is required to …

Porting a convolutional neural network for stereo vision in hardware

DOG Sotiropoulos… - 2020 25th International …, 2021 - ieeexplore.ieee.org
With the leaps of progress done in the field of machine learning through the last few years,
Artificial Neural Networks (ANN) are being used in more and more applications. In the field …

[PDF][PDF] Novel Neural Network Accelerator Architectures for FPGAs

M Kerner - digikogu.taltech.ee
E cient Hardware Architecture for Contractive Autoencoders.....................
Introduction...................................................................... ContractiveAutoencoder …

[PDF][PDF] FPGA TABANLI SAYISAL DEVRELER İÇİN SENTEZLENEBİLİR TAMSAYI ÇARPMA İŞLEMİ YAPAN IP ÇEKİRDEĞİ TASARIMI

S Dereli - researchgate.net
Özet Sayısal devrelerde çarpma işlemi mantık kapıları ve flip-floplarla gerçekleştirildiğinde
karmaşıklığı bit sayısı arttıkça üstel olarak artan bir işlemdir. O nedenle bir sayısal devre …