Energy-efficient runtime adaptable L1 STT-RAM cache design

K Kuan, T Adegbija - … on Computer-Aided Design of Integrated …, 2019 - ieeexplore.ieee.org
Much research has shown that applications have variable runtime cache requirements. In
the context of the increasingly popular spin-transfer torque RAM (STT-RAM) cache, the …

Compression-aware and performance-efficient insertion policies for long-lasting hybrid llcs

C Escuin, AA Khan, P Ibáñez, T Monreal… - … Symposium on High …, 2023 - ieeexplore.ieee.org
Emerging non-volatile memory (NVM) technologies can potentially replace large SRAM
memories such as the last-level cache (LLC). However, despite recent advances, NVMs …

L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime

C Escuin, P Ibáñez, D Navarro, T Monreal, JM Llabería… - Plos one, 2023 - journals.plos.org
Several emerging non-volatile (NV) memory technologies are rising as interesting
alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM …

STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption

C Escuín Blasco, T Monreal Arnal… - ACACES 2019: July …, 2019 - upcommons.upc.edu
Current applications demand larger on-chip memory capacity since off-chip memory
accesses be-come a bottleneck. However, if we want to achieve this by scaling down the …

L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime

C Escuin, P Ibañez, T Monreal, JM Llaberia… - arXiv preprint arXiv …, 2022 - arxiv.org
Several emerging non-volatile (NV) memory technologies are rising as interesting
alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM …

Crafting Non-Volatile Memory (NVM) Hierarchies: Optimizing Performance, Reliability, and Energy Efficiency

Crafting Non-Volatile Memory (NVM) Hierarchies: Optimizing Performance, Reliability, and
Energy Efficiency / Carlos Escuín Blas Page 1 2024 228 Carlos Escuín Blasco Crafting Non-Volatile …

[PDF][PDF] Crafting Non-Volatile Memory (NVM) Hierarchies: Optimizing Performance, Reliability, and Energy Efficiency

The escalating number of cores and accelerators in modern computing systems and the
huge memory footprints and requirements of emerging applications beckon new challenges …

[PDF][PDF] STT-RAM Memory Hierarchy Designs Aimed to Performance, Reliability and Energy Consumption

C Escuin, T Monreal, JM Llabería, V Viñals, P Ibáñez - core.ac.uk
Current applications demand larger on-chip memory capacity since off-chip memory
accesses become a bottleneck. However, if we want to achieve this by scaling down the …

Pronóstico de capacidad efectiva y prestaciones en una cache no volátil de último nivel

C Escuín Blasco, T Monreal Arnal… - … en arquitectura y …, 2021 - upcommons.upc.edu
La degradación debida a las escrituras que sufren las bitcells implementadas con tecnologi´
as de memoria no volátil (NVM) es uno de los principales escollos que se presentan a la …