False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

JJ Liou, A Krstic, LC Wang, KT Cheng - Proceedings of the 39th annual …, 2002 - dl.acm.org
We propose a false-path-aware statistical timing analysis framework. In our framework, cell
as well as interconnect delays are assumed to be correlated random variables. Our tool can …

Speed binning with path delay test in 150-nm technology

BD Cory, R Kapur, B Underwood - IEEE Design & Test of …, 2003 - ieeexplore.ieee.org
What would it take to reduce speed binning's dependency on functional testing? One
answer is a structural at-speed test approach that can achieve the same effectiveness as …

Critical path selection for delay fault testing based upon a statistical timing model

LC Wang, JJ Liou, KT Cheng - IEEE Transactions on Computer …, 2004 - ieeexplore.ieee.org
Critical path selection is an indispensable step for testing of small-size delay defects.
Historically, this step relies on the construction of a set of worst-case paths, where the timing …

Longest-path selection for delay test under process variation

X Lu, Z Li, W Qiu, DMH Walker… - IEEE Transactions on …, 2005 - ieeexplore.ieee.org
Under manufacturing process variation, a path through a net is called longest if there exists
a process condition under which the path has the maximum delay among all paths through …

Testing for transistor aging

AH Baba, S Mitra - 2009 27th IEEE VLSI Test Symposium, 2009 - ieeexplore.ieee.org
Transistor aging results in circuit delay degradation over time, and is a growing concern for
future systems. On-line circuit failure prediction, together with on-line self-test, can overcome …

Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices

JJ Liou, A Krstic, YM Jiang… - IEEE transactions on …, 2003 - ieeexplore.ieee.org
The performance of deep submicron designs can be affected by various parametric
variations, manufacturing defects, noise or modeling errors that are all statistical in nature. In …

Path selection for delay testing of deep sub-micron devices using statistical performance sensitivity analysis

JJ Liou, KT Cheng… - Proceedings 18th IEEE …, 2000 - ieeexplore.ieee.org
The performance of deep sub-micron designs can be affected by various parametric
variations, manufacturing defects, noise or even modeling errors that are all statistical in …

Testing of critical paths for delay faults

M Sharma, JH Patel - Proceedings International Test …, 2001 - ieeexplore.ieee.org
Testing the critical paths in a circuit is essential to cover distributed delay and small delay
defects in a manufactured circuit. However, in most circuits, only a small percentage of …

Adaptive testing: Conquering process variations

E Yilmaz, S Ozev, O Sinanoglu… - 2012 17th IEEE …, 2012 - ieeexplore.ieee.org
Increasing process variations result in increasing statistical diversity in manufactured
devices. Test plans that are developed without this diversity in mind are bound to result in …

On theoretical and practical considerations of path selection for delay fault testing

JJ Liou, LC Wang, KT Cheng - Proceedings of the 2002 IEEE/ACM …, 2002 - dl.acm.org
In current industrial practice, critical path selection is an indispensable step for AC delay test
and timing validation. Traditionally, this step relies on the construction of a set of worse-case …