In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to
model real-delay switching activity for power estimation is proposed. The logic circuit is …

Within this paper the gate-level power-simulation tool GliPS (Glitch Power Simulator) is
presented, which gives excellent accuracy (in the range of transistor-level simulators) at high …

Accurate estimation of switching activity is very important in digital circuits. In this paper we
present a comparison between the evaluation of the switching activity calculated using logic …

In this paper an enhanced gate-level power estimation tool with efficient glitch modeling is
presented. With little addition in computational cost from the traditional event driven …

Switching activity estimation is an important step in power estimation of digital VLSI circuits.
While simulation yields accurate results, it is time consuming. In this paper, we propose a …

The reduction of power and energy dissipation of digital circuits by optimisation of hardware
as well as software is a main target during the design of low power systems for signal …

The accurate calculation of a circuit's power consumption on gate level relies on an exact
analysis of a circuit's activity (net activities). In combinatorial parts of a circuit many …

This dissertation addresses the problem of dynamic power estimation and optimization in
the design of digital CMOS VLSI circuits. A Petri net based technique is proposed for …

Embedded processing and reconfigurable computing is a new paradigm based on
dynamically adapting the hardware to reconfigure the computation and communication …