A Critical Review of Finger Vein Recognition Techniques for Human Identification

R Kumar, V Bharti - 2021 Third International Conference on …, 2021 - ieeexplore.ieee.org
The specific parts of human body used for vein recognition are finger, palm, hand dorsal and
wrist. The merit of the popularity of a finger vein recognition method depends upon key …

[PDF][PDF] Comparison of instruction scheduling and register allocation for Mips And Hpl-Pd architecture for exploitation of instruction level parallelism

R Kumar - Engineering Heritage Journal, 2018 - researchgate.net
The integrated approaches for instruction scheduling and register allocation have been
promising area of research for code generation and compiler optimization. In this paper we …

An approach for compiler optimization to exploit instruction level parallelism

R Kumar, PK Singh - … Computing, Networking and Informatics-Volume 2 …, 2014 - Springer
Abstract Instruction Level Parallelism (ILP) is not the new idea. Unfortunately ILP
architecture not well suited to for all conventional high level language compilers and …

[PDF][PDF] Control Flow Prediction through Multiblock Formation in Parallel Register Sharing Architecture

R Kumar, PK Singh - Journal on Computer Science and …, 2010 - researchgate.net
In this paper we introduce control flow prediction (CFP) in parallel register sharing
architecture. The main idea behind this concept is to use a step beyond the prediction of …

[PDF][PDF] Role of multiblocks in Control Flow Prediction using Parallel Register Sharing Architecture

R Kumar, PK Singh - International Journal of Computer Applications, 2010 - Citeseer
In this paper we present control flow prediction (CFP) in parallel register sharing architecture
to achieve high degree of ILP. The main idea behind this concept is to use a step beyond the …

[PDF][PDF] INSTRUCTION LEVEL PARALLELISM–THE ROLE OF ARCHITECTURE AND COMPILER

R Kumar, PK Singh - Proceeding of ICETSTM, 2013 - researchgate.net
The instruction level parallelism (ILP) is not a new idea. It has been in practice since 1970
and became a much more significant force in computer design by 1980s. The researchers …

A Comparative Analysis of HPL-PD and MIPS Architectures by Using Integrated Approach for IS and RA for Exploiting ILP

R Kumar - International Journal of Service Science, Management …, 2019 - igi-global.com
In this article, the authors have proposed an integrated algorithm for instruction scheduling
and register allocation, and implemented it for compiler optimization in a machine …

A novel heuristic for selection of hyperblock in If-conversion

R Kumar, AK Saxena, PK Singh - 2011 3rd International …, 2011 - ieeexplore.ieee.org
In this paper we present a novel heuristic for selection of hyperblock in If-conversion. The if-
conversion has been applied to be promising method for exploitation of ILP in the presence …

[PDF][PDF] ILP Exploitation and Speedup Issues and Their Solutions through Balanced Scheduling

R Kumar, PK Singh - iieng.org
In this paper, we present issues associated with hardware and compiler to exploit instruction
level parallelism. In this reference the solutions related to balanced scheduling have been …

[PDF][PDF] Simulation of Branch Prediction Optimization in ParallelRegister Sharing Architecture

R Kumar, PK Singh - International Journal of Modeling and Optimization, 2012 - ijmo.org
In this paper we present simulation of optimization of branch prediction in parallel register
sharing architecture to show high degree of ILP. The main idea behind this concept is to use …