A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS

J Prinzie, M Steyaert, P Leroux… - 2016 IEEE Asian …, 2016 - ieeexplore.ieee.org
This paper presents a Single Event Upset (SEU) robust low phase-noise PLL for clock
generation in harsh environments like nuclear and space applications. The PLL has been …

Optically synchronized phased arrays in CMOS

M Gal-Katziri, C Ives, A Khakpour… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
Optical synchronization of large-span arrays offers significant benefits over electrical
methods in terms of the weight, cost, power dissipation, and complexity of the clock …

A 23–36.8-GHz low-noise frequency synthesizer with a fundamental colpitts VCO array in SiGe BiCMOS for 5G applications

Z Li, G Cheng, T Han, Z Li… - IEEE Transactions on Very …, 2020 - ieeexplore.ieee.org
This article describes a wideband low-noise frequency synthesizer implemented in 0.13-
SiGe BiCMOS process for 5G millimeter-wave applications. To extend the frequency range …

A Temperature Compensated Triple-Path PLL With Non-Linearity Desensitization Capable of Operating at 77 K

T Liu, X Wang, R Wang, G Wu… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
A novel triple-path PLL (TPPLL) is presented to compensate the VCO frequency drift caused
by the large temperature variations meanwhile maintaining a stable bandwidth and good …

A gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

C Chen, V Wallangen, D Gong, C Grace… - Journal of …, 2019 - iopscience.iop.org
This paper presents the design and simulation results of a gigabit transceiver Application
Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel …

A 210fs RMS jitter 187.5 MHz-3GHz fractional-N frequency synthesizer with quantization noise suppression techniques and chopping differential charge pump for …

H Li, Y Shen, T Wang, J Liu - Microelectronics Journal, 2019 - Elsevier
This paper proposes a low noise fractional-N frequency synthesizer with quantization noise
suppression techniques and a chopping differential charge pump. A level-shift-less phase …

20-GHz PLL-based configurable frequency generator in 180nm SiGe-on-SOI BiCMOS

JD Cali, CM Grens, SE Turner… - 2015 IEEE Radio …, 2015 - ieeexplore.ieee.org
This paper presents a configurable frequency generator (CFG) capable of synthesizing
frequencies between 10 MHz and 20 GHz with superior far-out phase noise of less than-150 …

Design of 0.35-ps RMS jitter 4.4–5.6-GHz frequency synthesizer with adaptive frequency calibration using 55-nm CMOS technology

Y Qiu, L Zhao, F Zhang - Circuits, Systems, and Signal Processing, 2018 - Springer
This paper demonstrates the design and implementation of a 5-GHz frequency synthesizer
using 55-nm complementary metal-oxide semiconductor technology. The proposed …

An 8.5–12.5 GHz multi-PLL clock architecture with LC PLL and Ring PLL for multi-lane multi-protocol SerDes

Y He, Z Wang, H Liu, F Lv, S Yuan… - … on electron devices …, 2017 - ieeexplore.ieee.org
This paper presents a multi-PLL clock architecture used in a 4-lane multi-protocol serial link
applications. The clock architecture consists of one public LC PLL and four standalone ring …

1.28 and 5.12 Gbps multi-channel twinax cable receiver ASICs for the ATLAS Inner Tracker Pixel Detector upgrade

C Chen, D Gong, S Hou, G Huang, X Huang… - Nuclear Instruments and …, 2020 - Elsevier
We present two prototypes of a gigabit transceiver ASIC, GBCR1 and GBCR2, both
designed in a 65-nm CMOS technology for the ATLAS Inner Tracker Pixel Detector readout …