Optical synchronization of large-span arrays offers significant benefits over electrical methods in terms of the weight, cost, power dissipation, and complexity of the clock …
Z Li, G Cheng, T Han, Z Li… - IEEE Transactions on Very …, 2020 - ieeexplore.ieee.org
This article describes a wideband low-noise frequency synthesizer implemented in 0.13- SiGe BiCMOS process for 5G millimeter-wave applications. To extend the frequency range …
T Liu, X Wang, R Wang, G Wu… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
A novel triple-path PLL (TPPLL) is presented to compensate the VCO frequency drift caused by the large temperature variations meanwhile maintaining a stable bandwidth and good …
C Chen, V Wallangen, D Gong, C Grace… - Journal of …, 2019 - iopscience.iop.org
This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel …
H Li, Y Shen, T Wang, J Liu - Microelectronics Journal, 2019 - Elsevier
This paper proposes a low noise fractional-N frequency synthesizer with quantization noise suppression techniques and a chopping differential charge pump. A level-shift-less phase …
JD Cali, CM Grens, SE Turner… - 2015 IEEE Radio …, 2015 - ieeexplore.ieee.org
This paper presents a configurable frequency generator (CFG) capable of synthesizing frequencies between 10 MHz and 20 GHz with superior far-out phase noise of less than-150 …
Y Qiu, L Zhao, F Zhang - Circuits, Systems, and Signal Processing, 2018 - Springer
This paper demonstrates the design and implementation of a 5-GHz frequency synthesizer using 55-nm complementary metal-oxide semiconductor technology. The proposed …
Y He, Z Wang, H Liu, F Lv, S Yuan… - … on electron devices …, 2017 - ieeexplore.ieee.org
This paper presents a multi-PLL clock architecture used in a 4-lane multi-protocol serial link applications. The clock architecture consists of one public LC PLL and four standalone ring …
C Chen, D Gong, S Hou, G Huang, X Huang… - Nuclear Instruments and …, 2020 - Elsevier
We present two prototypes of a gigabit transceiver ASIC, GBCR1 and GBCR2, both designed in a 65-nm CMOS technology for the ATLAS Inner Tracker Pixel Detector readout …