Systematic approach for state-of-the-art architectures and system-on-chip selection for heterogeneous IoT applications
R Krishnamoorthy, K Krishnan, B Chokkalingam… - IEEE …, 2021 - ieeexplore.ieee.org
The Internet of Things (IoT) refers to a network of physical devices, which collects data and
processes into a system without human intervention. In the commercialized market, IoT …
processes into a system without human intervention. In the commercialized market, IoT …
A multi-one instruction set computer for microcontroller applications
M Crepaldi, A Merello, M Di Salvo - IEEE Access, 2021 - ieeexplore.ieee.org
This work presents a simple integer-only instruction set architecture and microarchitecture
derived from One Instruction Set Computers (OISCs) and embedding multiple execution …
derived from One Instruction Set Computers (OISCs) and embedding multiple execution …
Automatic Generation of Simulators for Processors Enhanced for Security in Virtualization
SC Mhatre, P Chandran - IEEE Access, 2025 - ieeexplore.ieee.org
All new computer architectures need to be performance evaluated for acceptance and
simulation is the most widely used method for evaluation of new processor designs. Sharing …
simulation is the most widely used method for evaluation of new processor designs. Sharing …
Non-invasive intraoral stand-alone tongue control system based on RSIC-V edge computing
The intelligent tongue control system is of great significance for assisting the independent
life of patients with a limb disability. In order to more accurately control the assisted living …
life of patients with a limb disability. In order to more accurately control the assisted living …
Five-Stage Pipelined 32-Bit RISC-V Base Integer Instruction Set Architecture Soft Microprocessor Core in VHDL
AE Phangestu, IT Mujiono, MI Kom - … International Seminar on …, 2022 - ieeexplore.ieee.org
Proprietary technologies with complicated licensing currently dominate the microprocessor
industry. As a result, we must seek out a freely available, open-source alternative. In this …
industry. As a result, we must seek out a freely available, open-source alternative. In this …
Implementation of RISC-V Instruction Set Architecture for edge IoT computing platform
P Arul, N Abirami, S Sayeekumar… - … on Advances in …, 2024 - ieeexplore.ieee.org
The development of a fully synthesizable 32-bit processor using the open-source and free
RISC-V (RV32I) ISA is described in this work. Low Cost embedded devices were considered …
RISC-V (RV32I) ISA is described in this work. Low Cost embedded devices were considered …
ASIC design of a 32-bit low power RISC-V based system core for medical applications
G Kanase, M Nithin - 2021 6th international conference on …, 2021 - ieeexplore.ieee.org
The electronic devices play a decisive role in the realm of medical applications. The analysis
of medical images and axial tomography scanners are uses high performance processors …
of medical images and axial tomography scanners are uses high performance processors …
Design of Extended RISC-V for Q-Learning Hardware Accelerator using HW/SW Co-Design
I Syafalni, MS Mazaya, MR Elfazri… - 2024 IEEE Asia …, 2024 - ieeexplore.ieee.org
In this paper, we propose a novel RISC-V ISA extension for a reinforcement learning-based
hardware accelerator called RISC-Q. We introduce new instructions ie, q. store_constant, q …
hardware accelerator called RISC-Q. We introduce new instructions ie, q. store_constant, q …
GQoSMT: On Guaranteeing the Quality of Service Requirements of Simultaneous Multithreading Processors
Guaranteeing the quality of service of a running thread on a Simultaneous Multithreading
processor is one of the most challenging issues since these processors allow sharing of …
processor is one of the most challenging issues since these processors allow sharing of …
Design of 32-bit RISC V using area efficient multiplier based on homogeneous hybrid adder
G Sangeeth, D Jayanthi, K Kavitha… - AIP Conference …, 2023 - pubs.aip.org
Design of 32-bit RISC V Using Area Efficient Multiplier based on Homogeneous Hybrid Adder
Page 1 Design of 32-bit RISC V Using Area Efficient Multiplier based on Homogeneous Hybrid …
Page 1 Design of 32-bit RISC V Using Area Efficient Multiplier based on Homogeneous Hybrid …