Memory-efficient high-speed convolution-based generic structure for multilevel 2-D DWT

BK Mohanty, PK Meher - … on Circuits and Systems for Video …, 2012 - ieeexplore.ieee.org
In this paper, we have proposed a design strategy for the derivation of memory-efficient
architecture for multilevel 2-D DWT. Using the proposed design scheme, we have derived a …

Memory-efficient hardware architecture of 2-D dual-mode lifting-based discrete wavelet transform

CH Hsia, JS Chiang, JM Guo - IEEE Transactions on Circuits …, 2012 - ieeexplore.ieee.org
Memory requirements (for storing intermediate signals) and critical path are essential issues
for 2-D (or multidimensional) transforms. This paper presents new algorithms and hardware …

Memristor-based hardware accelerator for image compression

Y Halawani, B Mohammad, M Al-Qutayri… - … Transactions on Very …, 2018 - ieeexplore.ieee.org
Memristor-based hardware accelerators are gaining an increased attention as a potential
candidate to speed-up the vector-matrix operations commonly needed in many digital image …

Area-and power-efficient architecture for high-throughput implementation of lifting 2-D DWT

BK Mohanty, A Mahajan… - IEEE transactions on …, 2012 - ieeexplore.ieee.org
We have suggested a new data-access scheme for the computation of lifting two-
dimensional (2-D) discrete wavelet transform (DWT) without using data transposition. We …

SMFrWF: Segmented modified fractional wavelet filter: Fast low-memory discrete wavelet transform (DWT)

M Tausif, E Khan, M Hasan, M Reisslein - IEEE Access, 2019 - ieeexplore.ieee.org
This paper proposes a novel algorithm to compute the 2-D discrete wavelet transform (DWT)
of high-resolution (HR) images on low-cost visual sensor and Internet of Things (IoT) nodes …

A memory-efficient high-throughput architecture for lifting-based multi-level 2-D DWT

Y Hu, CC Jong - IEEE Transactions on signal processing, 2013 - ieeexplore.ieee.org
In this paper, we present a novel memory-efficient high-throughput scalable architecture for
multi-level 2-D DWT. We studied the existing DWT architectures and observed that data …

A memory-efficient scalable architecture for lifting-based discrete wavelet transform

Y Hu, CC Jong - IEEE Transactions on Circuits and Systems II …, 2013 - ieeexplore.ieee.org
In this brief, we propose a new parallel lifting-based 2-D DWT architecture with high memory
efficiency and short critical path. The memory efficiency is achieved with a novel scanning …

High-performance hardware architectures for multi-level lifting-based discrete wavelet transform

AD Darji, SS Kushwah, SN Merchant… - EURASIP Journal on …, 2014 - Springer
In this paper, three hardware efficient architectures to perform multi-level 2-D discrete
wavelet transform (DWT) using lifting (5, 3) and (9, 7) filters are presented. They are …

Approximate lifting 2-d dwt hardware design for image encoder of wireless visual sensors

BK Mohanty - IEEE Sensors Journal, 2023 - ieeexplore.ieee.org
In this article, a novel approximate hybrid multiplier design is proposed to reduce the data-
path width of lifting 2-D discrete wavelet transform (DWT) especially for wireless visual …

Hardware-efficient DWT architecture for image processing in visual sensors networks

A George - IEEE Sensors Journal, 2023 - ieeexplore.ieee.org
This article proposes a fractional wavelet filter (FrWF)-based 2-D discrete wavelet transform
(DWT) architecture for the 9/7 Cohen–Daubechies–Feauveau (CDF) filter employed at the …