The alpha 21264 microprocessor

RE Kessler - IEEE micro, 1999 - ieeexplore.ieee.org
Alpha microprocessors have been performance leaders since their introduction in 1992. The
first generation 21064 and the later 21164 raised expectations for the newest generation …

Memory dependence prediction using store sets

GZ Chrysos, JS Emer - ACM SIGARCH Computer Architecture News, 1998 - dl.acm.org
For maximum performance, an out-of-order processor must issue load instructions as early
as possible, while avoiding memory-order violations with prior store instructions that write to …

ProfileMe: Hardware support for instruction-level profiling on out-of-order processors

J Dean, JE Hicks, CA Waldspurger… - Proceedings of 30th …, 1997 - ieeexplore.ieee.org
Profile data is valuable for identifying performance bottlenecks and guiding optimizations.
Periodic sampling of a processor's performance monitoring hardware is an effective …

Checkpoint processing and recovery: Towards scalable large instruction window processors

H Akkary, R Rajwar… - Proceedings. 36th Annual …, 2003 - ieeexplore.ieee.org
Large instruction window processors achieve high performance by exposing large amounts
of instruction level parallelism. However, accessing large hardware structures typically …

The Alpha 21264 microprocessor architecture

RE Kessler, EJ McLellan… - … Conference on Computer …, 1998 - ieeexplore.ieee.org
The 21264 is the third generation Alpha microprocessor from Compaq Computer (formerly
Digital Equipment) Corporation. This microprocessor achieves the industry-leading …

Verification of an implementation of Tomasulo's algorithm by compositional model checking

KL McMillan - … Aided Verification: 10th International Conference, CAV' …, 1998 - Springer
An implementation of an out-of-order processing unit based on Tomasulo's algorithm is
formally verified using compositional model checking techniques. This demonstrates that …

A statistically rigorous approach for improving simulation methodology

JJ Yi, DJ Lilja, DM Hawkins - The Ninth International …, 2003 - ieeexplore.ieee.org
Due to cost, time, and flexibility constraints, simulators are often used to explore the design
space when developing new processor architectures, as well as when evaluating the …

The design space of register renaming techniques

D Sima - IEEE micro, 2000 - ieeexplore.ieee.org
Register renaming is a technique to remove false data dependencie-write after read (WAR)
and write after write (WAW)-that occur in straight line code between register operands of …

[图书][B] The computer engineering handbook

VG Oklobdzija - 2001 - taylorfrancis.com
There is arguably no field in greater need of a comprehensive handbook than computer
engineering. The unparalleled rate of technological advancement, the explosion of …

Micro-architectural simulation of in-order and out-of-order arm microprocessors with gem5

FA Endo, D Couroussé… - … conference on embedded …, 2014 - ieeexplore.ieee.org
Heterogeneous multicore systems have gained momentum, specially for embedded
applications, thanks to the performance and energy consumption trade-offs provided by …