High Current Density in Monolayer MoS2 Doped by AlOx
Semiconductors require stable doping for applications in transistors, optoelectronics, and
thermoelectrics. However, this has been challenging for two-dimensional (2D) materials …
thermoelectrics. However, this has been challenging for two-dimensional (2D) materials …
CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology
HH Radamson, Y Miao, Z Zhou, Z Wu, Z Kong, J Gao… - Nanomaterials, 2024 - mdpi.com
After more than five decades, Moore's Law for transistors is approaching the end of the
international technology roadmap of semiconductors (ITRS). The fate of complementary …
international technology roadmap of semiconductors (ITRS). The fate of complementary …
Low temperature characterization of 14nm FDSOI CMOS devices
M Shin, M Shi, M Mouis, A Cros, E Josse… - … Workshop on Low …, 2014 - ieeexplore.ieee.org
A detailed characterization of low temperature operation of n and p MOS devices from 14nm
FDSOI CMOS technology has been conducted. The transfer characteristics measured …
FDSOI CMOS technology has been conducted. The transfer characteristics measured …
Simulation study of a 3-D device integrating FinFET and UTBFET
By integrating 3-D nonplanar fins and 2-D ultrathin bodies, wavy FinFETs merge two
formerly competing technologies on a silicon-on-insulator platform to deliver enhanced …
formerly competing technologies on a silicon-on-insulator platform to deliver enhanced …
Impact of back gate bias on analog performance of dopingless transistor
R Kumar, M Panchore - Transactions on Electrical and Electronic Materials, 2023 - Springer
In this brief, the impact of back gate bias (V gb), on analog performance of silicon on
insulator dopingless transistor (SOI-DLT) is investigated. It is observed that SOI-DLTs are …
insulator dopingless transistor (SOI-DLT) is investigated. It is observed that SOI-DLTs are …
In depth characterization of electron transport in 14 nm FD-SOI CMOS devices
M Shin, M Shi, M Mouis, A Cros, E Josse, GT Kim… - Solid-State …, 2015 - Elsevier
In this paper, carrier transport properties in highly scaled (down to 14 nm-node) FDSOI
CMOS devices are presented from 77 K to 300 K. At first, we analyzed electron transport …
CMOS devices are presented from 77 K to 300 K. At first, we analyzed electron transport …
Planar fully-depleted-silicon-on-insulator technologies: Toward the 28 nm node and beyond
This paper presents a comprehensive overview of the research done in the last decade on
planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the frame of the joint …
planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the frame of the joint …
A mobility enhancement strategy for sub-14nm power-efficient FDSOI technologies
Continuous CMOS improvement has been achieved in recent years through strain
engineering for mobility enhancement. Nevertheless, as transistor pitch is scaled down …
engineering for mobility enhancement. Nevertheless, as transistor pitch is scaled down …
Total ionizing dose responses of forward body bias ultra-thin body and buried oxide FD-SOI transistors
Q Zheng, J Cui, L Xu, B Ning, K Zhao… - … on Nuclear Science, 2019 - ieeexplore.ieee.org
This paper investigates the total ionizing dose (TID) responses of forward body bias (FBB)
ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) transistors …
ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) transistors …
Investigation on performance degradation due to induced interface trapped charges on HSO based FDSOI NCFET and sustaining it through back-gate bias
RR Shaik, KP Pradhan - Semiconductor Science and Technology, 2022 - iopscience.iop.org
In this article, a variant of doped HfO 2 based ferroelectric capacitor ie silicon doped HfO 2
(hafnia-silica/HSO) is investigated for analytical feasibility and viability for negative …
(hafnia-silica/HSO) is investigated for analytical feasibility and viability for negative …