Full adder is one of the most important digital components for which many improvements
have been made to improve its architecture. In this paper, we present two new symmetric …

Robustness of high fan-in domino circuits is degraded by technology scaling due to
exponential increase in leakage. In this paper, we propose several domino logic circuit …

In this paper, a simple approach to reduce delay variations in domino logic gates is
proposed. Previous analysis by the same authors showed that delay variations in domino …

In this paper, a new charging scheme for reducing the power consumption of dynamic
circuits is presented. The proposed technique is suitable for large fan-in gates where the …

Clock Controlled Dual keeper Domino logic structures (CCDD _1 and CCDD _2) for
achieving a high‐speed performance with low power consumption and a good noise margin …

Aggressive scaling of single-gate CMOS device face greater challenge in nanometre
technology as sub-threshold and gate-oxide leakage currents increase exponentially with …

This paper presents low-power carbon nanotube field-effect transistor (CNTFET)-based
quaternary logic circuits. The proposed quaternary circuits are designed based on the …

Dynamic gates are preferred in the design of high-performance modules in modern
microprocessors due to the relatively high speed of dynamic gates compared with that of …

Power dissipation, propagation delay and noise are major issues in digital circuit design. In
this paper, a new leakage-tolerant domino circuit is presented which has lower power …

For computational arithmetic, a full adder is the primary logic units in VLSI applications. A
new full adder circuit design has been presented in this article which is based on input …