Field programmable gate array applications—A scientometric review

J Ruiz-Rosero, G Ramirez-Gonzalez, R Khanna - Computation, 2019 - mdpi.com
Field Programmable Gate Array (FPGA) is a general purpose programmable logic device
that can be configured by a customer after manufacturing to perform from a simple logic gate …

A custom parallel hardware architecture of nonlinear model-predictive control on fpga

F Xu, Z Guo, H Chen, D Ji, T Qu - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This article presents the field-programmable gate array (FPGA) implementation of a particle
swarm optimization (PSO)-based nonlinear model-predictive control (NMPC) for …

[PDF][PDF] Pipeline Implementation of the Unified CORDIC Algorithm in FPGA

WJ Pérez-Holguín… - Revista Facultad de …, 2023 - revistas.udea.edu.co
La implementación realizada calcula las funciones trigonométricas (seno, coseno y arco
tangente de dos parámetros) y las funciones hiperbólicas (seno hiperbólico, coseno …

Hardware efficient architecture for element-based lattice reduction aided k-best detector for MIMO systems

B Halak, M El-Hajjar, A Hassanein - Journal of Sensor and Actuator …, 2018 - mdpi.com
Multiple-Input Multiple-Output (MIMO) systems are characterised by increased capacity and
improved performance compared to the single-input single-output (SISO) systems. One of …

[PDF][PDF] Improving low latency applications for reconfigurable devices

S Denholm - 2023 - core.ac.uk
This thesis seeks to improve low latency application performance via architectural
improvements in reconfigurable devices. This is achieved by improving resource utilisation …

Maximising Parallel Memory Access for Low Latency FPGA Designs

S Denholm, W Luk - 2022 IEEE International Symposium on …, 2022 - ieeexplore.ieee.org
Memory-based computing stores pre-computed function results in memory to be read at
runtime. FPGAs group together multiple block memories (BRAMs) to form this memory, all …

Enhanced CORDIC algorithm using an area efficient carry select adder

SC Inguva, JB Seventline - 2017 International Conference on …, 2017 - ieeexplore.ieee.org
In this paper, we have designed an efficient CORDIC algorithm, which is used to minimize
the CORDIC rotation angle with the help of several rotations. The main idea of this new …

Multiplier-less hardware realization of trigonometric functions for high speed applications

D De, A Ghosh, KG Kumar, A Saha… - 2018 IEEE Applied …, 2018 - ieeexplore.ieee.org
This paper presents a unified architecture of trigonometric functions using CORDIC
algorithm and its implementation on FPGA. The hardware finds applications in fields of …

[PDF][PDF] Implementation of Area efficient CORDIC for QPSK Modulation

IS Chandra, JB Seventline - Journal of Engineering Science and …, 2018 - jestr.org
In this paper, we have designed a CORDIC algorithm, which is used to minimize the angle
with help of several rotations. In the process, we have used the proposed CORDIC algorithm …

A parallel and pipelined architecture for cordic algorithm

V Ellapan - International Journal of Advances in Signal and Image …, 2019 - xlescience.org
Abstract The COordinate Rotation DIgital Computer (CORDIC) algorithm is an efficient
algorithm to calculate the iteratively phase and magnitude or the vector rotations in linear …