Crystallinity of inorganic films grown by atomic layer deposition: Overview and general trends

V Miikkulainen, M Leskelä, M Ritala… - Journal of Applied …, 2013 - pubs.aip.org
Atomic layer deposition (ALD) is gaining attention as a thin film deposition method, uniquely
suitable for depositing uniform and conformal films on complex three-dimensional …

Interfacial chemistry of oxides on InxGa (1− x) As and implications for MOSFET applications

CL Hinkle, EM Vogel, PD Ye, RM Wallace - Current Opinion in Solid State …, 2011 - Elsevier
The prospect of enhanced device performance from III–V materials has been recognized for
at least 50years, and yet, relative to the phenomenal size of the Si-based IC industry, these …

Interface engineering and chemistry of Hf-based high-k dielectrics on III–V substrates

G He, X Chen, Z Sun - Surface Science Reports, 2013 - Elsevier
Recently, III–V materials have been extensively studied as potential candidates for post-Si
complementary metal-oxide-semiconductor (CMOS) channel materials. The main obstacle …

A Distributed Model for Border Traps in MOS Devices

Y Yuan, L Wang, B Yu, B Shin, J Ahn… - IEEE Electron …, 2011 - ieeexplore.ieee.org
A distributed border trap model based on tunneling between the semiconductor surface and
trap states in the gate dielectric film is formulated to account for the observed frequency …

Ultimate scaling of CMOS logic devices with Ge and III–V materials

M Heyns, W Tsai - Mrs bulletin, 2009 - cambridge.org
Over the years, many new materials have been introduced in advanced complementary
metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the …

A Distributed Bulk-Oxide Trap Model for InGaAs MOS Devices

Y Yuan, B Yu, J Ahn, PC McIntyre… - … on Electron Devices, 2012 - ieeexplore.ieee.org
This paper presents a distributed circuit model for bulk-oxide traps based on tunneling
between the semiconductor surface and trap states in the gate dielectric film. The model is …

A systematic study of (NH4) 2S passivation (22%, 10%, 5%, or 1%) on the interface properties of the Al2O3/In0. 53Ga0. 47As/InP system for n-type and p-type In0 …

É O'Connor, B Brennan, V Djara, K Cherkaoui… - Journal of Applied …, 2011 - pubs.aip.org
In this work, we present the results of an investigation into the effectiveness of varying
ammonium sulphide (NH 4) 2 S concentrations in the passivation of n-type and p-type In …

Simplified Surface Preparation for GaAs Passivation Using Atomic Layer-Deposited High- Dielectrics

Y Xuan, HC Lin, DY Peide - IEEE Transactions on electron …, 2007 - ieeexplore.ieee.org
Atomic layer deposition (ALD) provides a unique opportunity to integrate high-quality gate
dielectrics on III-V compound semiconductors. The physics and chemistry of a III-V …

Atomic layer deposition of dielectrics on Ge and III–V materials for ultrahigh performance transistors

RM Wallace, PC McIntyre, J Kim, Y Nishi - MRS bulletin, 2009 - cambridge.org
The prospect of utilizing alternative transistor channel materials for ultrahigh performance
transistors will require suitable gate dielectrics for surface-channel field-effect devices. With …

Border traps in Ge/III–V channel devices: Analysis and reliability aspects

E Simoen, DHC Lin, A Alian… - … on Device and …, 2013 - ieeexplore.ieee.org
The aim of this review paper is to describe the impact of so-called border traps (BTs) in high-
k gate oxides on the operation and reliability of high-mobility channel transistors. First, a …