Lithography hotspot detection: From shallow to deep learning
As VLSI technology nodes continue, the gap between lithography system manufacturing
ability and transistor feature size induces serious problems, thus lithography hotspot …
ability and transistor feature size induces serious problems, thus lithography hotspot …
ePlace-3D: Electrostatics based placement for 3D-ICs
We propose a flat, analytic, mixed-size placement algorithm ePlace-3D for three-dimension
integrated circuits (3D-ICs) using nonlinear optimization. Our contributions are (1) …
integrated circuits (3D-ICs) using nonlinear optimization. Our contributions are (1) …
Design-phase buffer allocation for post-silicon clock binning by iterative learning
At submicrometer manufacturing technology nodes, process variations affect circuit
performance significantly. To counter these variations, engineers are reserving more timing …
performance significantly. To counter these variations, engineers are reserving more timing …
Accelerating chip design with machine learning: From pre-silicon to post-silicon
At sub-22nm regime, chip designs have to go through hundreds to thousands of steps and
tasks before shipment. Many tasks are data and simulation intensive, thereby demanding …
tasks before shipment. Many tasks are data and simulation intensive, thereby demanding …
Generative adversarial network based scalable on-chip noise sensor placement
The relentless efforts towards power reduction of integrated circuits have led to the
prevalence of near-threshold computing paradigms. With the significantly reduced noise …
prevalence of near-threshold computing paradigms. With the significantly reduced noise …
Power management for multicore processors via heterogeneous voltage regulation and machine learning enabled adaptation
X Zhan, J Chen… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
This work is based on the vision that the ultimate power integrity and efficiency may be best
achieved via a heterogeneous chain of voltage processing starting from onboard switching …
achieved via a heterogeneous chain of voltage processing starting from onboard switching …
Machine learning for noise sensor placement and full-chip voltage emergency detection
Power supply fluctuation can be potential threat to the correct operations of processors, in
the form of voltage emergency that happens when supply voltage drops below a certain …
the form of voltage emergency that happens when supply voltage drops below a certain …
A statistical methodology for noise sensor placement and full-chip voltage map generation
Noise margin violation, also known as voltage emergency induced by continuously reducing
noise margin and increasing magnitude of current swings, is becoming a severe threat to the …
noise margin and increasing magnitude of current swings, is becoming a severe threat to the …
On the deployment of on-chip noise sensors
Runtime noise management systems can enforce power integrity without significantly
increasing design margins. These systems typically respond to on-chip noise sensors to …
increasing design margins. These systems typically respond to on-chip noise sensors to …
Full-Chip Voltage Prediction via Graph Attention Based Neural Networks
Y Li, P Zhou - 2023 IEEE 15th International Conference on …, 2023 - ieeexplore.ieee.org
Power supply noise has been a rising threat to the normal functioning of a microprocessor in
the form of voltage emergence. The state-of-the-art commercial chips detect such …
the form of voltage emergence. The state-of-the-art commercial chips detect such …