System and method for generating flat layout

A Ginetti - US Patent 8,255,845, 2012 - Google Patents
The present invention provides a method for generating flat layout design view that
comprises importing port definitions of a first hierarchical block of digital instances from a …

Lithographic hotspot detection using multiple machine learning kernels

CC Chiang, YT Yu, GH Lin, HR Jiang - US Patent App. 14/287,921, 2014 - Google Patents
A hotspot detection system that classifies a set of hotspot training data into a plurality of
hotspot clusters according to their topologies, where the hotspot clusters are associated with …

Computer-aided-design tools for reducing power consumption in programmable logic devices

DIM Milton, D Neto, V Betz - US Patent 7,555,741, 2009 - Google Patents
5,677,522 A* 10/1997 Rice et al.................... 235.454 5,748,490 A* 5/1998 Viot et
al....................... T16/3 6,038,386 A 3/2000 Jain............................ T16, 16 6,275,969 B1* 8/2001 …

Placement of structured nets

CJ Alpert, MC Kim, Z Li, N Viswanathan… - US Patent …, 2014 - Google Patents
BACKGROUND The present application relates generally to an improved data processing
apparatus and method and more specifically to mechanisms for providing improved …

Concurrent placement and routing using hierarchical constraints

LE Henrickson, LC Lim - US Patent 8,667,444, 2014 - Google Patents
BACKGROUND Automated integrated circuit design has traditionally addressed placement
and routing as independent and sepa rable processes. For example, a circuit placement …

Partitioning for hardware-accelerated functional verification

MD Moffitt, MA Sustik, PG Villarrubia - US Patent 8,327,304, 2012 - Google Patents
(57) ABSTRACT A circuit design is partitioned for hardware-accelerated func tional
verification using a directed hypergraph with edge weights that are a function of slack. Slack …

Method, system, and computer program product for implementing routing aware placement or floor planning for an electronic design

R Ruehl, H Yu, JA Baudhuin - US Patent 10,515,177, 2019 - Google Patents
Disclosed are techniques for implementing routing aware floorplanning or placement for an
electronic design. These techniques preprocess an electronic design and a plurality of …

Integrated circuits having in-situ constraints

QD Qian - US Patent 10,216,890, 2019 - Google Patents
In accordance with the present method and system for improving integrated circuit layout, a
local process modification is calculated from simulated process response variables at a set …

Generation of independent logical and physical hierarchy

EP Huijbregts, A Dey - US Patent 8,549,461, 2013 - Google Patents
(57) ABSTRACT A logically hierarchical netlist may be split along physical partition
boundaries while retaining information on the logi cal hierarchy. Nets can be driven to …

Multilevel IC floorplanner

SC Lin, TC Chen, YW Chang - US Patent 7,603,640, 2009 - Google Patents
To generate a floorplan for an integrated circuit to be formed by a collection of modules
interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned …