Design of the ultra low-power synchronizer using ADCL buffer for adiabatic logic
SI Cho, T Harada, M Yokoyama - IEICE Electronics Express, 2012 - jstage.jst.go.jp
The adiabatic dynamic CMOS logic (ADCL) has been studied to reduce the power
dissipation in conventional CMOS logic. The clock signal of logic circuits should be …
dissipation in conventional CMOS logic. The clock signal of logic circuits should be …
[PDF][PDF] Optimization of control block of 3-bit PWM using adiabatic dynamic CMOS logic for OLED illumination system based on internet of things service
SI Cho, SD Yeo, SK Kim, M Yokoyama - International Journal of Smart …, 2016 - gvpress.com
The environment development for deep sleep has been studied using analysis results of the
big data about vital signs and parameters in the bedroom. The organic light emitting diode …
big data about vital signs and parameters in the bedroom. The organic light emitting diode …
Design of low-power clock generator synchronized with the AC power source using the ADCL buffer for adiabatic logics
SI Cho, SK Kim, T Harada… - The Journal of the Korea …, 2012 - koreascience.kr
In this paper, the low-power clock generator synchronized with the AC power signal using
the adiabatic dynamic CMOS logic (ADCL) buffer is proposed for adiabatic logics. To reduce …
the adiabatic dynamic CMOS logic (ADCL) buffer is proposed for adiabatic logics. To reduce …
Low‐Power Supply Circuit Using Off‐Chip Resonant Circuit for Adiabatic Logic
Y Takahashi, H Sato - Electronics and Communications in …, 2015 - Wiley Online Library
This paper presents a low‐power sinusoidal supply circuit for our proposed adiabatic logic
(2PC2AL). The proposed supply circuit consists of three parts: LC resonant circuit, voltage …
(2PC2AL). The proposed supply circuit consists of three parts: LC resonant circuit, voltage …
Optimized Design of Low-power Adiabatic Dynamic CMOS Logic Digital 3-bit PWM for SSL Dimming System
SI Cho, M Mizunuma, M Yokoyama - IEIE Transactions on Smart …, 2013 - koreascience.kr
The size and power consumption of digital circuits including the dimming circuit part will
increase for high-performance solid state lighting (SSL) systems in the future. This study …
increase for high-performance solid state lighting (SSL) systems in the future. This study …
Combined mixer and filter circuitry
U Özdemir - US Patent 11,671,057, 2023 - Google Patents
A combined mixer and filter circuitry is disclosed. The combined mixer and filter circuitry
comprises a mixer comprising a first input, a second input and an output. The combined …
comprises a mixer comprising a first input, a second input and an output. The combined …
Combined mixer and filter circuitry
U Özdemir - US Patent 11,201,589, 2021 - Google Patents
A combined mixer and filter circuitry is disclosed. The combined mixer and filter circuitry
comprises a mixer comprising a first input, a second input and an output. The combined …
comprises a mixer comprising a first input, a second input and an output. The combined …
[PDF][PDF] Supply clock generation (driver) circuit for 2PASCL: Hara active inductor equivalent circuit and simulation
N Anuar - nazrulanuar.com
The paper presents a split-level sinusoidal power supply clock generator circuit for Two-
Phase Adiabatic Static CMOS Logic circuit (2PASCL). The driving of adiabatic logic requires …
Phase Adiabatic Static CMOS Logic circuit (2PASCL). The driving of adiabatic logic requires …
[PDF][PDF] Supply clock (driver) circuit for 2PASCL: nMOS circuit characteristic prior to Hara active inductor simulation
N Anuar - nazrulanuar.com
The paper presents a split-level sinusoidal power supply clock circuit for Two-Phase
Adiabatic Static CMOS Logic circuit (2PASCL). We investigate the most suitable scheme …
Adiabatic Static CMOS Logic circuit (2PASCL). We investigate the most suitable scheme …
능동인덕터로구성한전하회수회로를위한전원클럭발생기
김진우 - 2013 - s-space.snu.ac.kr
오늘날 VLSI 시스템에는 고성능과 저전력이라는 두 가지 주제가 일반적으로 다루어 진다.
시스템의 동작 주파수가 증가함에 따라 시스템의 높은 성능을 위해 시스템의 소비 전력 또한 …
시스템의 동작 주파수가 증가함에 따라 시스템의 높은 성능을 위해 시스템의 소비 전력 또한 …