Modeling and circuit synthesis for independently controlled double gate FinFET devices
Independent control of front and back gate in double gate (DG) devices can be used to
merge parallel transistors in noncritical paths. This reduces the effective switching …
merge parallel transistors in noncritical paths. This reduces the effective switching …
A new algorithm for simultaneous gate sizing and threshold voltage assignment
Y Liu, J Hu - Proceedings of the 2009 international symposium on …, 2009 - dl.acm.org
Gate sizing and threshold voltage (V t) assignment are popular techniques for circuit timing
and power optimization. Existing methods, by and large, are either sensitivity-driven …
and power optimization. Existing methods, by and large, are either sensitivity-driven …
[图书][B] Timing optimization through clock skew scheduling
The results of the various clock skew scheduling methodologies described in this research
monograph are presented in this chapter. Results of each application are presented in …
monograph are presented in this chapter. Results of each application are presented in …
Sensitivity-guided metaheuristics for accurate discrete gate sizing
The well-studied gate-sizing optimization is a major contributor to IC power-performance
tradeoffs. Viable optimizers must accurately model circuit timing, satisfy a variety of …
tradeoffs. Viable optimizers must accurately model circuit timing, satisfy a variety of …
Aging-aware timing analysis and optimization considering path sensitization
KC Wu, D Marculescu - 2011 Design, Automation & Test in …, 2011 - ieeexplore.ieee.org
Device aging, which causes significant loss on circuit performance and lifetime, has been a
main factor in reliability degradation of nanoscale designs. Aggressive technology scaling …
main factor in reliability degradation of nanoscale designs. Aggressive technology scaling …
A comparison of two approaches for combining the votes of cooperating classifiers
J Franke, E Mandler - 11th IAPR International Conference on Pattern …, 1992 - computer.org
CMOS remains the mainstream IC technology and optimization of digital CMOS circuits is a
major focus of research. This paper presents a comprehensive model for estimation and …
major focus of research. This paper presents a comprehensive model for estimation and …
Gate sizing for cell library-based designs
With increasing time-to-market pressure and shortening semiconductor product cycles, more
and more chips are being designed with library-based methodologies. In spite of this shift …
and more chips are being designed with library-based methodologies. In spite of this shift …
Logic synthesis for low power
L Benini, G De Micheli - Logic Synthesis and Verification, 2002 - Springer
Energy-efficient design of integrated circuits requires specialized tools and technologies.
This chapter surveys some of the most important contributions in logic synthesis for …
This chapter surveys some of the most important contributions in logic synthesis for …
Gate sizing and device technology selection algorithms for high-performance industrial designs
It is becoming more and more important to design high performance designs with as low
power as possible. In this paper, we study the gate sizing and device technology selection …
power as possible. In this paper, we study the gate sizing and device technology selection …
Combating NBTI degradation via gate sizing
X Yang, K Saluja - … on Quality Electronic Design (ISQED'07), 2007 - ieeexplore.ieee.org
NBTI is becoming one of the dominant circuit reliability concerns in nano-scale technologies.
We believe that designers can combat NBTI degradation using appropriate circuit …
We believe that designers can combat NBTI degradation using appropriate circuit …