A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars
This article describes a 10-GHz chirp generator for frequency-modulated continuous-wave
(FMCW) radars, that is based on a digital PLL (DPLL) with a two-point injection of the …
(FMCW) radars, that is based on a digital PLL (DPLL) with a two-point injection of the …
A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a 62.1-dBc Fractional Spur
This article presents a 7-GHz fractional-N digital phase-locked loop (DPLL) without any
digital pre-distortion (DPD) on the integral nonlinearity (INL) of the digital-to-time converter …
digital pre-distortion (DPD) on the integral nonlinearity (INL) of the digital-to-time converter …
A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm
This work presents a fractional-N digital phase-locked loop (DPLL) characterized by low
jitter and small area, featuring fast multi-variable calibration. To minimize the use of silicon …
jitter and small area, featuring fast multi-variable calibration. To minimize the use of silicon …
Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop
Parasitic coupling between the building blocks within a fractional-N phase-locked loop (PLL)
can result in noticeable spurs in its output spectrum, thus affecting the PLL's usability in …
can result in noticeable spurs in its output spectrum, thus affecting the PLL's usability in …
A Low-Noise Fractional- Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC
This work presents a digital-to-time converter (DTC)-based fractional-phase-locked loop
(PLL) achieving low jitter and low spurs. Thanks to the proposed resistor-based inverse …
(PLL) achieving low jitter and low spurs. Thanks to the proposed resistor-based inverse …
A Low-Jitter Fractional- Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC
This article presents a fractional-digital-to-time converter (DTC)-based digital phase-locked
loop (PLL), achieving simultaneously low phase noise and low spurious tones. The PLL …
loop (PLL), achieving simultaneously low phase noise and low spurious tones. The PLL …
A Dual-Alternating-Slope Digital-to-Time Converter Leveraging Mismatch to Improve Delay Step Size
N Jain, EAM Klumperink, H van Rumpt… - IEEE Journal of Solid …, 2024 - ieeexplore.ieee.org
This article introduces a dual-alternating-slope digital-to-time converter (DASDTC) topology
that reduces the dependency of DTC delay on component values and power supply. A …
that reduces the dependency of DTC delay on component values and power supply. A …
A Harmonic-Mixer-Based Fractional-N PLL Employing Voltage-Domain Feed-Forward Noise Cancellation
H Zhang, M Osada, Y Zhu… - IEEE Journal of Solid-State …, 2024 - ieeexplore.ieee.org
A harmonic-mixer (HM)-based fractional-N phase-locked loop (PLL) employing voltage-
domain feed-forward noise cancellation (FFNC) is presented in this article. By adding the …
domain feed-forward noise cancellation (FFNC) is presented in this article. By adding the …
Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation
Y Hu, W Tao, RB Staszewski - IEEE Open Journal of the Solid …, 2024 - ieeexplore.ieee.org
A fractional-N frequency synthesizer with low total jitter [eg,< 50fsrms, accounting for both
phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high …
phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high …
Digital Phase-Locked Loops: Exploring Different Boundaries
This article examines the research area of digital phase-locked loops (DPLLs), a critical
component in modern electronic systems, from wireless communication devices to RADAR …
component in modern electronic systems, from wireless communication devices to RADAR …