[PDF][PDF] Low power residue number system using lookup table decomposition and finite state machine based post computation

B Morasa, P Nimmagadda - Indonesian Journal of Electrical …, 2022 - academia.edu
In this paper, memory optimization and architectural level modifications are introduced for
realizing the low power residue number system (RNS) with improved flexibility for …

FPGA implementation of high performance digital FIR filter design using a hybrid adder and multiplier

V Thamizharasan, N Kasthuri - International Journal of Electronics, 2023 - Taylor & Francis
The energetic growth in portable multimedia and mobile communication system has
increased the requirement of high-speed signal processing system with compact area and …

Low-complexity filter for software-defined radio by modulated interpolated coefficient decimated filter in a hybrid Farrow

TO Otunniyi, HC Myburgh - Sensors, 2022 - mdpi.com
Realising a low-complexity Farrow channelisation algorithm for multi-standard receivers in
software-defined radio is a challenging task. A Farrow filter operates best at low frequencies …

An integrated FIR adaptive filter design by hybridizing canonical signed digit (CSD) and approximate booth recode (ABR) algorithm in DA architecture for the reduction …

N Arumugam, B Paramasivan - Multidimensional Systems and Signal …, 2021 - Springer
Abstract The Finite Impulse Response (FIR) filter plays an important role in many signal
processing applications. This manuscript proposes an intuitive adaptive filter based on fixed …

FIR filter realization via deferred end-around carry modular addition

A Belghadr, G Jaberipur - … on Circuits and Systems I: Regular …, 2018 - ieeexplore.ieee.org
Hardware realization of FIR filters that are based on residue number systems leads to
increased speed and reduced power, where besides the popular Mersenne numbers …

Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

V Thamizharasan, V Parthipan - Scientific Reports, 2024 - nature.com
In signal processing applications, the multipliers are essential component of arithmetic
functional units in many applications, like digital signal processors, image/video processing …

Design and implementation of AD9361-based software radio receiver

F Tian, H Li, L Yuan - EURASIP Journal on Wireless Communications and …, 2019 - Springer
Existing software radio platforms constructed by discrete devices have many disadvantages,
such as high power consumption, high cost, and poor portability. In this study, an AD9361 …

A new approach for 1-D and 2-D DWT architectures using LUT based lifting and flipping cell

G Hegde, KS Reddy, TKS Ramesh - AEU-International Journal of …, 2018 - Elsevier
In this paper, area and power efficient lifting and flipping discrete wavelet transform (DWT)
architectures are proposed. DWT architectural metrics such as critical path delay, area of …

Balanced Adders for Moduli Set

G Jaberipur, B Nadimi - … Transactions on Circuits and Systems I …, 2020 - ieeexplore.ieee.org
Residue number systems (RNS) are characterized by fast modular arithmetic and low power
dissipation. Numerous RNS applications take advantage of moduli set τ={2 n-1, 2 n, 2 n+ 1} …

Efficient variable-coefficient RNS-FIR filters with no restriction on the moduli set

A Belghadr, G Jaberipur - Signal, Image and Video Processing, 2022 - Springer
Introduction of residue number systems (RNS) into hardware realization of high dynamic
range FIR filters is known to be advantageous. However, deciding on the number and forms …