H Qian, H Liang, CH Chang… - 2013 18th Asia and …, 2013 - ieeexplore.ieee.org
This paper presents a fast and accurate steady state thermal simulator for heatsink and microfluid-cooled 3D-ICs. This model considers the thermal effect of TSVs at fine-granularity …
SK Millican, KK Saluja - 2012 IEEE 21st Asian Test Symposium, 2012 - ieeexplore.ieee.org
With technology scaling towards smaller geometries, the power density of modern integrated circuits (ICs) can potentially result into high temperatures during test, a problem further …
P Ghosal, SP Mohanty - 2015 IEEE International Symposium …, 2015 - ieeexplore.ieee.org
Power consumption and thereby the power minimization strategies in different steps of design of nanoelectronic circuits is a raising concern today. Memristors with its inherent low …
Summary form only given. We post-process images compressed by lossy JPEG algorithms (DCT and LOGO), following decompression, using Bezier polynomials for enhancement …
D Roy, P Ghosal - … Conference on Fuzzy Systems (FUZZ-IEEE), 2013 - ieeexplore.ieee.org
In DSM (deep sub-micron) regime, together with the integration density interconnects play a dominant role during layout design of integrated circuits. It eventually increases the …
D Roy, P Ghosal, N Das - Proceedings of the 2014 IEEE …, 2014 - ieeexplore.ieee.org
During recent days, the large problem space of very large scale integrated (VLSI) circuits has led global routing problem to a NP Complete one. With the advent of three dimensional …
The high integration density interconnects, closerproximity of modules, and the routing phase are pivotal during the layout of 3D ICs. Heuristic based approaches are typically used …
SR Choudhury, SN Pradhan - IEEE Access, 2020 - ieeexplore.ieee.org
Since hotspots and temperature gradients are reliability and performance-critical issues in processors, thermal awareness finds a vital place in the processor design cycle …