Thermal placement on PCB of components including 3D ICs

Y Satomi, K Hachiya, T Kanamoto… - IEICE Electronics …, 2020 - jstage.jst.go.jp
In this letter, we propose a method for optimizing the thermal placement of heat and non-
heat generating electronic components on a printed circuit board (PCB). Use a genetic …

Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects

H Qian, H Liang, CH Chang… - 2013 18th Asia and …, 2013 - ieeexplore.ieee.org
This paper presents a fast and accurate steady state thermal simulator for heatsink and
microfluid-cooled 3D-ICs. This model considers the thermal effect of TSVs at fine-granularity …

Linear programming formulations for thermal-aware test scheduling of 3D-stacked integrated circuits

SK Millican, KK Saluja - 2012 IEEE 21st Asian Test Symposium, 2012 - ieeexplore.ieee.org
With technology scaling towards smaller geometries, the power density of modern integrated
circuits (ICs) can potentially result into high temperatures during test, a problem further …

Power minimization of a memristor-based Wien bridge oscillator through a Simscape framework

P Ghosal, SP Mohanty - 2015 IEEE International Symposium …, 2015 - ieeexplore.ieee.org
Power consumption and thereby the power minimization strategies in different steps of
design of nanoelectronic circuits is a raising concern today. Memristors with its inherent low …

Post-processing enhancement of decompressed images using variable order Bezier polynomials and distance transform

J Mayer, GG Langdon - Proceedings DCC'98 Data …, 1998 - ieeexplore.ieee.org
Summary form only given. We post-process images compressed by lossy JPEG algorithms
(DCT and LOGO), following decompression, using Bezier polynomials for enhancement …

A fuzzified approach towards global routing in VLSI layout design

D Roy, P Ghosal - … Conference on Fuzzy Systems (FUZZ-IEEE), 2013 - ieeexplore.ieee.org
In DSM (deep sub-micron) regime, together with the integration density interconnects play a
dominant role during layout design of integrated circuits. It eventually increases the …

A thermal and congestion driven global router for 3D integrated circuits

D Roy, P Ghosal, N Das - Proceedings of the 2014 IEEE …, 2014 - ieeexplore.ieee.org
During recent days, the large problem space of very large scale integrated (VLSI) circuits
has led global routing problem to a NP Complete one. With the advent of three dimensional …

FuzzRoute: A method for thermally efficient congestion free global routing in 3D ICs

D Roy, P Ghosal, SP Mohanty - 2014 IEEE Computer Society …, 2014 - ieeexplore.ieee.org
The high integration density interconnects, closerproximity of modules, and the routing
phase are pivotal during the layout of 3D ICs. Heuristic based approaches are typically used …

使用功率密度緩和的方式應用於熱感知擺放的優化

羅仁國, 陳宏明 - 2012 - ir.lib.nycu.edu.tw
在此篇論文中, 熱感知擺放的問題被重新審視. 在先前的研究中, 主要著重於全域擺放(global
placement) 階段, 且效能通常是和擺置器(placer) 相關. 在此篇研究中溫度緩和的技術在後擺放 …

An Improved Matrix Generation Framework for Thermal Aware Placement in VLSI

SR Choudhury, SN Pradhan - IEEE Access, 2020 - ieeexplore.ieee.org
Since hotspots and temperature gradients are reliability and performance-critical issues in
processors, thermal awareness finds a vital place in the processor design cycle …