Frequency and time domain models are developed for backplane (BP), printed circuit board (PCB), and silicon interposer (SI) links using six-port transfer matrices (ABCD matrices) for …
Circuit-level models are developed to determine the upper bound on the performance of a 3- D IC link with through silicon vias (TSVs). It is shown that the performance of a 3-D link is …
In this study, we are pursuing an ultra low-loss interconnect pathway for 3D chip-chip connectivity, incorporating air-clad planar interconnects, air-clad TSVs, and gradual vertical …
V Kumar, R Sharma, J Chen, A Kapoor… - 2012 IEEE …, 2012 - ieeexplore.ieee.org
In this paper we present a compact model for analysis of 3D chip-to-chip interconnect pathways consisting of planar transmission lines, vias, package and pin discontinuities. The …
JW Holloway, R Han - US Patent 10,587,026, 2020 - Google Patents
Embodiments herein relate to a fully integrated broadband interconnect. The system comprises a first integrated circuit, a second integrated circuit, and a coupler structure to …
R Sharma, R Saha, PA Kohl - High-Speed Photonics …, 2017 - taylorfrancis.com
Modern electronic systems are composed of a dense fabric of interconnected lines that connect the electronic devices on a chip and chips on boards. The scaling of transistors to …
S Rakheja - IET Cyber‐Physical Systems: Theory & …, 2018 - Wiley Online Library
Graphene‐based heterostructures provide a viable platform to implement optoelectronic devices that can operate in the terahertz (THz) band. In this study, the authors focus on …