In nano-scale CMOS technologies, storage cells such as latches are becoming increasingly
sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. In the context …

This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS
technology. The latch comprises three interlocked single-node-upset-resilient cells and each …

Single event upsets (SEU) and single event transients (SET) are major reliability concerns in
deep submicron technologies. As technology feature size shrinks, digital circuits are …

In this paper, three high performance, low cost and robust latches (referred to as HLR, HLR-
CG1, and HLR-CG2) are proposed in 45 nm CMOS technology. The proposed latches are …

This article presents an energy-efficient triple-node-upset (TNU)-tolerant latch in a
subthreshold/near-threshold regime. The proposed latch provides the TNU tolerance using …

First, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUCT) latch,
featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with a C-element …

This paper presents and analyzes a high performance latch tolerating single event upsets
(SEU) in 45 nm CMOS technology. The internal nodes of the latch are immune to SEUs by …

This brief presents a double-node upset (DNU) self-recoverable latch design for high
performance and low power application. The latch is mainly constructed from eight mutually …

As a consequence of technology scaling down, gate capacitances and stored charge in
sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to …

As basic components, optimizing power consumption of flip-flops (FFs) can significantly
reduce the power of digital systems. In this article, an energy-efficient retentive true-single …