Apparatuses and methods for generating multiple row hammer address refresh sequences.
An example apparatus may include an address scrambler and a refresh control circuit. The …

Apparatuses and methods for selective row refreshes are disclosed herein. An example
apparatus may include a refresh control circuit. The refresh control circuit may be configured …

Apparatuses and methods for targeted row refreshes are disclosed herein. In an example
apparatus, a predecoder receives a target row address and determines whether a target row …

Apparatuses and methods for targeted row refreshes are disclosed herein. In an example
apparatus, a predecoder receives a target row address and determines whether a target row …

Apparatuses and methods for selective row refreshes are disclosed herein. An example
apparatus may include a refresh control circuit. The refresh control circuit may be configured …

The address of victim rows may be determined based on rows that are accessed in a
memory. The victim addresses may be stored and associated with a count for every time a …

Embodiments of the disclosure are drawn to apparatuses and methods for analog row
access tracking. A plurality of unit cells are provided, each of which contains one or more …

An example apparatus according to an aspect of the present disclosure includes an address
scrambler circuit including a sub-wordline scrambler circuit configured to receive a first …

Embodiments of the disclosure are drawn to apparatuses, systems, and methods for analog
row access rate determi nation. Accesses to different row addresses may be tracked by …

Embodiments of the disclosure are drawn to apparatuses and methods for managing access
counts of wordlines of a memory. Repeated access to an aggressor wordline may cause …