Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
JT Kavalieros, JK Brask, BS Doyle, U Shah… - US Patent …, 2009 - Google Patents
US7479421B2 - Process for integrating planar and non-planar CMOS transistors on a bulk
substrate and article made thereby - Google Patents US7479421B2 - Process for integrating …
substrate and article made thereby - Google Patents US7479421B2 - Process for integrating …
Multi-gate devices for the 32 nm technology node and beyond
Due to the limited control of the short channel effects, the high junction leakage caused by
band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling …
band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling …
Double patterning scheme for sub-0.25 k1 single damascene structures at NA= 0.75, λ= 193nm
M Maenhoudt, J Versluijs, H Struyf… - Optical …, 2005 - spiedigitallibrary.org
Using 193nm lithography at NA= 0.75, the minimum pitch that can be obtained in a single
exposure is 160nm for dark field structures that are used in single damascene interconnect …
exposure is 160nm for dark field structures that are used in single damascene interconnect …
SRAM cells and arrays
JJ Liaw - US Patent 8,987,831, 2015 - Google Patents
BACKGROUND Semiconductor devices are used in a variety of electronic applications, such
as personal computers, cellphones, digital cameras, and other electronic equipment, as …
as personal computers, cellphones, digital cameras, and other electronic equipment, as …
Reliability modeling and analysis of hot-carrier degradation in multiple-fin SOI n-channel FinFETs with self-heating
A comprehensive study on hot-carrier degradation (HCD) mechanisms in 14 nm silicon-on-
insulator (SOI) n-channel FinFETs is presented. The impact of high-frequency AC stress bias …
insulator (SOI) n-channel FinFETs is presented. The impact of high-frequency AC stress bias …
A look into the future of nanoelectronics
G Declerck - Digest of Technical Papers. 2005 Symposium on …, 2005 - ieeexplore.ieee.org
On the occasion of the 25th anniversary of the VLSI Symposium, it is appropriate to reflect on
the past and peer into the future. It is clear that continuing scaling in the coming decade is no …
the past and peer into the future. It is clear that continuing scaling in the coming decade is no …
Demonstration of highly scaled FinFET SRAM cells with high-κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond
H Kawasaki, M Khater, M Guillorn… - 2008 IEEE …, 2008 - ieeexplore.ieee.org
Highly scaled FinFET SRAM cells, of area down to 0.128 m 2, were fabricated using high-
kappa dielectric and a single metal gate to demonstrate cell size scalability and to …
kappa dielectric and a single metal gate to demonstrate cell size scalability and to …
A junctionless accumulation mode NC-FinFET gate underlap design for improved stability and self-heating reduction
A novel metal ferroelectric insulator semiconductor (MFIS)-type junctionless accumulation
mode (JAM) negative capacitance (NC)-FinFET with reduced self-heating is proposed for …
mode (JAM) negative capacitance (NC)-FinFET with reduced self-heating is proposed for …
Performance improvement of tall triple gate devices with strained SiN layers
N Collaert, A De Keersgieter, KG Anil… - IEEE electron device …, 2005 - ieeexplore.ieee.org
In this letter, we investigate the influence of tensile and compressive SiN layers on the
device performance of triple-gate devices with 60-nm fin height and fin widths down to 35 …
device performance of triple-gate devices with 60-nm fin height and fin widths down to 35 …
Impact of hot-carrier degradation on drain-induced barrier lowering in multifin SOI n-channel FinFETs with self-heating
Application of high-frequency ac stress in the place of conventional dc stress is known to
decrease the damage caused by self-heating (SH)-induced hot-carrier injection (HCI) in …
decrease the damage caused by self-heating (SH)-induced hot-carrier injection (HCI) in …