[图书][B] Statistical analysis and optimization for VLSI: Timing and power

A Srivastava, D Sylvester, D Blaauw - 2006 - books.google.com
Statistical Analysis and Optimization For VLSI: Timing and Power is a state-of-the-art book
on the newly emerging field of statistical computer-aided design (CAD) tools. The very latest …

Subthreshold leakage modeling and reduction techniques

J Kao, S Narendra, A Chandrakasan - Proceedings of the 2002 IEEE …, 2002 - dl.acm.org
As technology scales, subthreshold leakage currents grow exponentially and become an
increasingly large component of total power dissipation. CAD tools to help model and …

Design and optimization of multithreshold CMOS (MTCMOS) circuits

M Anis, S Areibi, M Elmasry - IEEE Transactions on Computer …, 2003 - ieeexplore.ieee.org
Reducing power dissipation is one of the most important issues in very large scale
integration design today. Scaling causes subthreshold leakage currents to become a large …

Full-chip analysis of leakage power under process variations, including spatial correlations

H Chang, SS Sapatnekar - Proceedings of the 42nd Annual Design …, 2005 - dl.acm.org
In this paper, we present a method for analyzing the leakage current, and hence the leakage
power, of a circuit under process parameter variations that can include spatial correlations …

Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

M Anis, M Mahmoud, M Elmasry, S Areibi - Proceedings of the 39th …, 2002 - dl.acm.org
Reducing power dissipation is one of the most principle subjects in VLSI design today.
Scaling causes subthreshold leakage currents to become a large component of total power …

Gate oxide leakage current analysis and reduction for VLSI circuits

D Lee, D Blaauw, D Sylvester - IEEE Transactions on Very …, 2004 - ieeexplore.ieee.org
In this paper we address the growing issue of gate oxide leakage current (I/sub gate/) at the
circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a …

Statistical analysis of subthreshold leakage current for VLSI circuits

R Rao, A Srivastava, D Blaauw… - IEEE Transactions on …, 2004 - ieeexplore.ieee.org
We develop a method to estimate the variation of leakage current due to both intra-die and
inter-die gate length process variability. We derive an analytical expression to estimate the …

[图书][B] Low-power electronics design

C Piguet - 2018 - books.google.com
The power consumption of integrated circuits is one of the most problematic considerations
affecting the design of high-performance chips and portable devices. The study of power …

Pushing ASIC performance in a power envelope

R Puri, L Stok, J Cohn, D Kung, D Pan… - Proceedings of the 40th …, 2003 - dl.acm.org
Power dissipation is becoming the most challenging design constraint in nanometer
technologies. Among various design implementation schemes, standard cell ASICs offer the …

Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization

D Nguyen, A Davare, M Orshansky… - Proceedings of the …, 2003 - dl.acm.org
We describe an optimization strategy for minimizing total power consumption using dual
threshold voltage (Vth) technology. Significant power savings are possible by simultaneous …