Buffers in on-chip networks consume significant energy, occupy chip area, and increase
design complexity. In this paper, we make a case for a new approach to designing on-chip …

This paper studies the impact of L2 cache sharing on threads that simultaneously share the
cache, on a chip multi-processor (CMP) architecture. Cache sharing impacts threads …

While scalable coherence has been extensively studied in the context of general purpose
chip multiprocessors (CMPs), GPU architectures present a new set of challenges …

Many future shared-memory multiprocessor servers will both target commercial workloads
and use highly-integrated" glueless" designs. Implementing low-latency cache coherence in …

In the many-core era, scalable coherence and on-chip interconnects are crucial for shared
memory processors. While snoopy coherence is common in small multicore systems …

Multi-threaded commercial workloads implement many important Internet services.
Consequently, these workloads are increasingly used to evaluate the performance of …

To maintain coherence in conventional shared-memory multiprocessor systems, processors
first check other processors' caches before obtaining data from memory. This coherence …

Research on Cyber Physical Systems (CPS) has led to quite a number of astonishing
technical solutions that are becoming standard in many application domains affecting our …

Realizing scalable cache coherence in the many-core era comes with a whole new set of
constraints and opportunities. It is widely believed that multi-hop, unordered on-chip …

As the core count in shared-memory manycores keeps increasing, it is becoming
increasingly harder to design cache-coherence protocols that deliver high performance …