Resp: A nonintrusive transaction-level reflective mpsoc simulation platform for design space exploration

G Beltrame, L Fossati, D Sciuto - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
This paper presents reflective simulation platform (ReSP), a transaction-level multiprocessor
simulation platform based on the integration of SystemC and Python. ReSP exploits the …

[PDF][PDF] A Proposed virtualization technique to enhance IT Services

N El-Khameesy, HAR Mohamed - International Journal of Information …, 2012 - academia.edu
System virtualization is an antique art that will continue as long as applications need
isolation and performance independence. Virtualization provides many benefits and greater …

High level power and energy exploration using ArchC

T Gupta, C Bertolini, O Héron… - 2010 22nd …, 2010 - ieeexplore.ieee.org
With the increase in the design complexity of MPSoC architectures, estimating power
consumption is very complex and time consuming at lower level of abstraction. We propose …

An esl approach for energy consumption analysis of cache memories in soc platforms

AG Silva-Filho, FR Cordeiro, CC Araujo… - International Journal …, 2011 - Wiley Online Library
The design of complex circuits as SoCs presents two great challenges to designers. One is
the speeding up of system functionality modeling and the second is the implementation of …

[图书][B] Multicore Technology: Architecture, Reconfiguration, and Modeling

MY Qadri, SJ Sangwine - 2018 - books.google.com
The saturation of design complexity and clock frequencies for single-core processors has
resulted in the emergence of multicore architectures as an alternative design paradigm …

Towards a Parameterizable cycle-accurate ISS in ArchC

C Bechara, N Ventroux… - ACS/IEEE International …, 2010 - ieeexplore.ieee.org
With the increase in the design complexity of MP-SoC architectures, flexible and accurate
processor simulators became a necessity for exploring the vast design space solutions. In …

On the simulation of HCI-induced variations of IC timings at high level

O Heron, C Bertolini, C Sandionigi, N Ventroux… - Journal of Electronic …, 2013 - Springer
Die shrinking combined with the non-ideal scaling of voltage increases the probability of
MOS transistors to encounter HCI. This mechanism causes timing degradation and possibly …

A proposed novel description language in digital system modeling

P Horváth, G Hosszú, F Kovács - Encyclopedia of Information …, 2015 - igi-global.com
The increasing complexity of data-processing systems forced the design methodologies to
move to a higher abstraction level (Shin, Gerstlauer, Dömer & Gajski, 2008) than the …

[PDF][PDF] From Intel VT-x to MIPS: An ArchC-based Model to Understanding the Hardware Virtualization Support

MK Ferreira, HC Freitas… - Workshop on Computer …, 2008 - researchgate.net
Due to the benefits provided by virtualization and parallel processing, such as concurrent
execution of multiple operating systems, the performance of servers has grown a lot. Intel VT …

Application capturing and performance estimation in an holistic design environment

M Rashid, B Pottier - … and Workshop on the Engineering of …, 2009 - ieeexplore.ieee.org
The objective of the hArtes (Holistic Approach to Reconfigurable real Time Embedded
Systems) is to provide a tool set that facilitates the management of entire design flow …