Writing applications that benefit from the massive computational power of future multicore
chip multiprocessors will not be an easy task for mainstream programmers accustomed to …

Performance loss due to long-latency memory accesses can be reduced by servicing
multiple memory accesses concurrently. The notion of generating and servicing long-latency …

A major shift from compute-centric to data-centric computing systems can be perceived, as
novel big data workloads like cognitive computing and machine learning strongly enforce …

General purpose hybrid dataflow/von-Neumann architectures are gaining attraction as
effective parallel platforms. Although different implementations differ in the way they merge …

The memristor-based neuromorphic computing system (NCS) with emerging storage and
computing integration architecture has drawn extensive attention. Because of the unique …

Due to the ability to store data and process information, the memristor-based neuromorphic
system has attracted extensive attention. Its efficient parallel computing approach allows it to …

This paper presents Simultaneous Speculative Threading (SST), which is a technique for
creating high-performance area-and power-efficient cores for chip multiprocessors. SST …

It is difficult to improve the single-thread performance of a processor in memory-intensive
programs because processors have hit the memory wall, ie, the large speed discrepancy …

Conventional load/store queues (LSQs) are an impediment to both power-efficient execution
in superscalar processors and scaling tolarge-window designs. In this paper, we propose …

Multiprocessors are coming into wide-spread use in many application areas, yet there are a
number of challenges to achieving a good tradeoff between complexity and performance …