Method for decoding data in non-volatile storage using reliability metrics based on multiple reads

N Mokhlesi, H Chin, D Zhao - US Patent 7,904,793, 2011 - Google Patents
Data stored in non-volatile storage is decoded using iterative probabilistic decoding and
multiple read operations to achieve greater reliability. An error correcting code such as a low …

Soft bit data transmission for error correction control in non-volatile memory

N Mokhlesi, H Chin, D Zhao - US Patent 7,966,550, 2011 - Google Patents
Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An
error correcting code such as a low density parity check code may be used. In one …

Integrated circuit routing with compaction

M Waller - US Patent 8,332,799, 2012 - Google Patents
An iterative technique is used to automatically route nets and alter spacing of an integrated
circuit design to achieve a fully routed and compact result. After identifying solid and hollow …

Non-volatile memory with soft bit data transmission for error correction control

N Mokhlesi, H Chin, D Zhao - US Patent 7,966,546, 2011 - Google Patents
Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An
error correcting code such as a low density parity check code may be used. In one …

Automatically routing nets with variable spacing

J Birch, M Waller, G Balsdon - US Patent 8,095,903, 2012 - Google Patents
(63) Continuation-in-part of application No. 10/709,843,(74) Attorney, Agent, or Firm—Aka
Chan LLP filed on Jun. 1, 2004, now Pat. No. 7,131,096, and a continuation-in-part of …

Method and apparatus for placing circuit modules

S Teig, JL Ganley - US Patent 7,055,120, 2006 - Google Patents
23 Design Automation Conference, 1986, pp. 708–714. Fang, S. et al., Constrained Via
Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Prob lems, 28." …

High-speed shape-based router

J Birch - US Patent 9,245,082, 2016 - Google Patents
A high-speed shape-based router is applicable to standard-cell digital designs, chip-level-
block assembly designs, and other styles of design. In a flow of the invention, the technique …

Non-volatile memory with guided simulated annealing error correction control

H Chin, N Mokhlesi - US Patent 7,975,209, 2011 - Google Patents
Data in non-volatile storage is decoded using iterative probabilistic decoding. An error
correcting code such as a low density parity check code may be used. In one approach …

Method of automatically routing nets according to parasitic constraint rules

J Birch, M Waller, M Williams, G Balsdon… - US Patent …, 2008 - Google Patents
US7363607B2 - Method of automatically routing nets according to parasitic constraint rules
- Google Patents US7363607B2 - Method of automatically routing nets according to …

Method and apparatus for computing placement costs

S Teig, JL Ganley - US Patent 7,080,336, 2006 - Google Patents
US7080336B2 - Method and apparatus for computing placement costs - Google Patents
US7080336B2 - Method and apparatus for computing placement costs - Google Patents Method …