Major advances have been made in the processing technologies of through-silicon-vias
(TSVs) because TSV is an essential element for both wafer-level 3-D integration and …

This paper proposes an equivalent lumped element model for various multi-TSV
arrangements and introduces closed form expressions for the capacitive, resistive, and …

This paper presents a design and modeling methodology of vertical interconnects for three-
dimensional integration (3DI) applications. Compact semi-analytical wideband circuit level …

According to the International Technology Roadmap for Semiconductors (ITRS), the
traditional scaling will no longer meet the performance and integration requirements of …

This paper presents the results obtained from the simulation of TSV structures in face-to-
back stacked dice. A novel simulation tool enabling device and electromagnetic (EM) co …

Abstract Three-dimensional (3D) integration, which stacks and connects function blocks
vertically, can overcome some physical/technological/economic limits encountered in planar …

This work addresses parasitic substrate coupling effects in 3D integrated circuits due to
Through Silicon Vias (TSV). Electrical characterizations have been performed on dedicated …

Ubiquitous mobile communication creates an increasing demand for high data rates,
complex modulation schemes and low power design. The cost and performance benefits of …

This paper discusses substrate coupling effects in 3D integrated circuits carried by TSV
interconnects (Through Silicon Vias). These electrical couplings lead to several impacts on …

Beginning with the invention of the first Integrated Circuit (IC) by Kilby and Noyce in 1959,
performance growth in IC is realized primarily by geometrical scaling, which has resulted in …