Pushing the level of abstraction of digital system design: A survey on how to program fpgas

ED Sozzo, D Conficconi, A Zeni, M Salaris… - ACM Computing …, 2022 - dl.acm.org
Field Programmable Gate Arrays (FPGAs) are spatial architectures with a heterogeneous
reconfigurable fabric. They are state-of-the-art for prototyping, telecommunications …

Matraptor: A sparse-sparse matrix multiplication accelerator based on row-wise product

N Srivastava, H Jin, J Liu, D Albonesi… - 2020 53rd Annual …, 2020 - ieeexplore.ieee.org
Sparse-sparse matrix multiplication (SpGEMM) is a computation kernel widely used in
numerous application domains such as data analytics, graph processing, and scientific …

Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations

A Izraelevitz, J Koenig, P Li, R Lin… - 2017 IEEE/ACM …, 2017 - ieeexplore.ieee.org
Enabled by modern languages and retargetable compilers, software development is in a
virtual “Cambrian explosion” driven by a critical mass of powerfully parameterized libraries; …

Tensaurus: A versatile accelerator for mixed sparse-dense tensor computations

N Srivastava, H Jin, S Smith, H Rong… - … Symposium on High …, 2020 - ieeexplore.ieee.org
Tensor factorizations are powerful tools in many machine learning and data analytics
applications. Tensors are often sparse, which makes sparse tensor factorizations memory …

Towards developing high performance RISC-V processors using agile methodology

Y Xu, Z Yu, D Tang, G Chen, L Chen… - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
While research has shown that the agile chip design methodology is promising to sustain
the scaling of computing performance in a more efficient way, it is still of limited usage in …

Review of neural network model acceleration techniques based on FPGA platforms

F Liu, H Li, W Hu, Y He - Neurocomputing, 2024 - Elsevier
Neural network models, celebrated for their outstanding scalability and computational
capabilities, have demonstrated remarkable performance across various fields such as …

Predictable accelerator design with time-sensitive affine types

R Nigam, S Atapattu, S Thomas, Z Li, T Bauer… - Proceedings of the 41st …, 2020 - dl.acm.org
Field-programmable gate arrays (FPGAs) provide an opportunity to co-design applications
with hardware accelerators, yet they remain difficult to program. High-level synthesis (HLS) …

Ultra-elastic cgras for irregular loop specialization

C Torng, P Pan, Y Ou, C Tan… - 2021 IEEE International …, 2021 - ieeexplore.ieee.org
Reconfigurable accelerator fabrics, including coarse-grain reconfigurable arrays (CGRAs),
have experienced a resurgence in interest because they allow fast-paced software algorithm …

OpenCGRA: An open-source unified framework for modeling, testing, and evaluating CGRAs

C Tan, C Xie, A Li, KJ Barker… - 2020 IEEE 38th …, 2020 - ieeexplore.ieee.org
Coarse-grained reconfigurable arrays (CGRAs), loosely defined as arrays of functional units
(eg, adder, subtractor, multiplier, divider, or larger multi-operation units, but smaller than a …

A pythonic approach for rapid hardware prototyping and instrumentation

J Clow, G Tzimpragos, D Dangwal… - … Conference on Field …, 2017 - ieeexplore.ieee.org
We introduce PyRTL, a Python embedded hardware design language that helps concisely
and precisely describe digital hardware structures. Rather than attempt to infer a good …