A high psrr, stable cmos current reference using process insensitive tc of resistance for wide temperature applications

A Jain, A Ali, S Kiran, Z Abbas - 2019 IEEE International …, 2019 - ieeexplore.ieee.org
In this paper, a highly stable all CMOS current reference against temperature and supply
variation is proposed. Current reference of 5μA and 50nA has been designed for low power …

A 1.2-V 2.18-ppm/° C curvature-compensated CMOS bandgap reference

Y Zhang, J Li, X Wang, Z Luo, Y Zhou - IEICE Electronics Express, 2021 - jstage.jst.go.jp
A high-precision and low-temperature-coefficient bandgap voltage reference is proposed in
0.11 μm CMOS process. A temperature piecewise compensation circuit is added to a …

A low temperature coefficient wide temperature range bandgap reference with high power supply rejection

J Qu, C Wu - IEICE Electronics Express, 2023 - jstage.jst.go.jp
This paper presents a low temperature coefficient and wide temperature range bandgap
reference with high power supply rejection. High temperature curvature compensation of this …

A 2.1-ppm/° C all-MOSFET voltage reference with a 1.2-V supply voltage

H Xu, Y Zhang, K Liang, J Hu, C Lu, G Li - IEICE Electronics Express, 2018 - jstage.jst.go.jp
This paper presents an ultra-low temperature coefficient subthreshold voltage reference,
which is based on a novel compensation principle without using any resistors or operational …

A 77-nA and three-output CMOS voltage reference with-73dB PSRR for energy harvesting systems

J Yang, Y Zeng, W Chen, Y Lin, H Zhi… - 2021 IEEE International …, 2021 - ieeexplore.ieee.org
A CMOS-only and multiple-output voltage reference has been proposed and simulated in a
standard 0.18 μm CMOS process in this paper. Three reference voltages with their own …

Performance optimization for the CMOS voltage reference circuit based on NSGA-II

H Huang, Y Zeng, J Liao, R Chen… - 2018 IEEE Asia Pacific …, 2018 - ieeexplore.ieee.org
An application of NSGA-II for parameter optimization in the design of a CMOS voltage
reference circuit is presented in this paper. It is difficult by manual work to design the optimal …

A 2.2 ppm/° C compensated bandgap voltage reference with a double-ended current trimming technique

W Yu, L He, J Xi, Q Sun, C Men - IEICE Electronics Express, 2022 - jstage.jst.go.jp
This paper presents a high-precision bandgap voltage reference (BGR) with a double-
ended current trimming technique. A high-order curvature compensation method is adopted …

3.75ppm/°C, -91dB PSRR, 27nW, 0.9V PVT Invariant Voltage Reference for Implantable Biomedical Applications

M Kelam, BY Battu, Z Abbas - … on VLSI Design and 2020 19th …, 2020 - ieeexplore.ieee.org
This brief presents a CMOS-only ultra low power voltage reference of 0.925 V which is
designed and simulated in TSMC 180nm technology. Current mixing between Self-Biased …

A 1.8-nW sub-1-V self-biased sub-bandgap reference for low-power systems

J Hu, K Liang, J Wang, G Li - IEICE Electronics Express, 2021 - jstage.jst.go.jp
An ultra-low power sub-bandgap voltage reference circuit fabricated in a standard 0.18-µm
CMOS technology is proposed. Exploiting the negative temperature characteristics ofVBE …

Automatic structure generation and parameter optimization for cmos voltage reference circuit

J Li, Y Zeng, J Wang, J Liao, J Yang, HZ Tan - IEEE Access, 2020 - ieeexplore.ieee.org
An automatic design system for the voltage reference circuit is presented in this paper. The
circuit coding method based on tracking coding is improved and the instruction set is …