A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level
As the trend of technology shrinking continues a vast amount of processors are being
incorporated in a limited space. Due to this almost half of the chip area in Multi-Processor …
incorporated in a limited space. Due to this almost half of the chip area in Multi-Processor …
Bandwidth-constrained multi-objective segmented brute-force algorithm for efficient mapping of embedded applications on NoC architecture
Network-on-chip (NoC) is an emerging alternative to address the communication problem in
embedded system-on-chip designs. One of the key and major issues is the optimized …
embedded system-on-chip designs. One of the key and major issues is the optimized …
An efficient algorithm for mapping real time embedded applications on NoC architecture
Network-on-chip (NoC) has appeared to be an impending substitute for the communication
paradigm in modern very large scale integration embedded systems. Apart from many …
paradigm in modern very large scale integration embedded systems. Apart from many …
[HTML][HTML] A network adaptive fault-tolerant routing algorithm for demanding latency and throughput applications of network-on-a-chip designs
Scalability is a significant issue in system-on-a-chip architectures because of the rapid
increase in numerous on-chip resources. Moreover, hybrid processing elements demand …
increase in numerous on-chip resources. Moreover, hybrid processing elements demand …
Prime turn model and first last turn model: an adaptive deadlock free routing for network-on-chips
Abstract Purpose: Network-on-Chips (NoCs) have emerged as a valuable solution for the
never-ending communication needs of large System-on-Chips (SoCs). It opened the doors …
never-ending communication needs of large System-on-Chips (SoCs). It opened the doors …
[HTML][HTML] Design and reliability analysis of a novel redundancy topology architecture
F Li, W Liu, W Gao, Y Liu, Y Hu - Sensors, 2022 - mdpi.com
Topology architecture has a decisive influence on network reliability. In this paper, we
design a novel redundancy topology and analyze the structural robustness, the number of …
design a novel redundancy topology and analyze the structural robustness, the number of …
An efficient algorithm for reliability evaluation of the bus network
F Li, W Liu - IEEE Access, 2022 - ieeexplore.ieee.org
The bus network is widely used in industrial automation and avionics systems due to its
many advantages. Network reliability is an important indicator of the bus network design and …
many advantages. Network reliability is an important indicator of the bus network design and …
Design and evaluation of binary-tree based scalable 2D and 3D network-on-chip architecture
Abstract Network-on-Chip (NoC) has been developed as a most prevailing innovation in the
paradigm of communication-centric technology. It solves the limitations of bus-based …
paradigm of communication-centric technology. It solves the limitations of bus-based …
[HTML][HTML] A low latency and low power indirect topology for on-chip communication
This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology
for on-chip communication. Main aspects of this work are the description of the architectural …
for on-chip communication. Main aspects of this work are the description of the architectural …
Hy-BTree: An efficient Tree based topology for FPGA based NoC implementation
BMP Prasad, K Parane… - 2021 IEEE International …, 2021 - ieeexplore.ieee.org
Due to their hierarchical structure, Binary Tree (BTree) topology can be employed in
Network-on-Chip (NoC) applications. Because of its lower bisection bandwidth, the …
Network-on-Chip (NoC) applications. Because of its lower bisection bandwidth, the …