Processor security: Detecting microarchitectural attacks via count-min sketches

K Arıkan, A Palumbo, L Cassano… - … Transactions on Very …, 2022 - ieeexplore.ieee.org
The continuous quest for performance pushed processors to incorporate elements such as
multiple cores, caches, acceleration units, or speculative execution that make systems very …

Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses

A Palumbo, M Ottavi, L Cassano - 2023 IEEE International …, 2023 - ieeexplore.ieee.org
Hardware Trojan Horses (HTHs) are today a serious issue for both academy and industry
because of their dramatic complexity and dangerousness. Indeed, it has been shown that …

A Wireless Data and Power Transfer-Enabled MCU for Shape-Configurable Chiplet-Based Computers

J Kadomoto, H Irie, S Sakai - 2024 IEEE Asia Pacific …, 2024 - ieeexplore.ieee.org
In this paper, we propose a shape-configurable chiplet-based computer for the easy
construction of embedded computing systems with diverse functions and shapes. Adjacent …

A Sound and Complete Algorithm for Code Generation in Distance-Based ISA

S Sugita, T Koizumi, R Shioya, H Irie… - Proceedings of the 32nd …, 2023 - dl.acm.org
The single-thread performance of a processor core is essential even in the multicore era.
However, increasing the processing width of a core to improve the single-thread …

An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS

T Amano, J Kadomoto, S Mitsuno… - … on Circuits and …, 2023 - ieeexplore.ieee.org
The single-thread performance of a CPU is an essential factor in a computer system.
However, increasing the processing width of a CPU to improve performance often results in …

[PDF][PDF] MEng Individual Project

S Wu, P Kelly, H Pirk - 2022 - imperial.ac.uk
In modern computer architecture, out-of-order superscalar processors use complex register
rename logic to remove false data dependencies between instructions and improve …

Strong ordered transaction for DMA transfers

K Xu, R Diamant, I Minkin… - US Patent …, 2025 - freepatentsonline.com
A technique for processing strong ordered transactions in a direct memory access engine
may include retrieving a memory descriptor to perform a strong ordered transaction, and …

ユーザの支援を用いたファジングによるハードウェアテスト

杉山優一, 塩谷亮太 - 研究報告組込みシステム(EMB), 2022 - ipsj.ixsq.nii.ac.jp
論文抄録 ハードウェアのバグや脆弱性は発見が難しい一方で, 製造後の修正も極めて困難である.
このため, そのようなバグや脆弱性を事前に見つけるためのテスト手法が多く提案されてきた …

ソフトプロセッサの相互検証に関するケーススタディ

松川達哉, 藤枝直輝 - 研究報告組込みシステム(EMB), 2021 - ipsj.ixsq.nii.ac.jp
論文抄録 ソフトプロセッサの検証では, しばしばプロセッサシミュレータとソフトプロセッサとの間で
命令実行結果を比較することが行われる. システムコールを含み, ファイルなどを扱う実用的な …